2010 IEEE International Test Conference最新文献_第8页

A kernel-based approach for functional test program generation 一种基于内核的功能测试程序生成方法

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699216

Po-Hsien Chang, Li-C. Wang, J. Bhadra

引用次数: 5

Is test power reduction through X-filling good enough? 通过x填充降低测试功率是否足够好?

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699297

F. Wu, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A. Virazel, M. Tehranipoor, K. Miyase, X. Wen, N. Ahmed

引用次数: 11

Mutation-based diagnostic test generation for hardware design error diagnosis 基于突变的硬件设计错误诊断测试生成

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699307

Shujun Deng, K. Cheng, Jinian Bian, Zhiqiu Kong

引用次数: 4

Automated test program generation for automotive devices 自动测试程序生成汽车设备

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699253

A. Drappa, Peter Huber, Jon Vollmar

引用次数: 1

Shadow checker (SC): A low-cost hardware scheme for online detection of faults in small memory structures of a microprocessor 影子检查器(SC):一种低成本的硬件方案，用于在线检测微处理器小内存结构中的故障

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699222

Rance Rodrigues, S. Kundu, O. Khan

{"title":"Shadow checker (SC): A low-cost hardware scheme for online detection of faults in small memory structures of a microprocessor","authors":"Rance Rodrigues, S. Kundu, O. Khan","doi":"10.1109/TEST.2010.5699222","DOIUrl":"https://doi.org/10.1109/TEST.2010.5699222","url":null,"abstract":"At various stages of a product life, faults arise from different sources. During product bring up, logic errors are dominant. During production, manufacturing defects are main concerns while during operation, the concern shifts to aging defects. No matter what the source is, debugging such defects may permit logic, circuit or physical design changes to eliminate them in future. Within a processor chip, there are three broad categories of structures, namely the large memory structures such as caches, small memory structures such as reorder buffer, issue queue, and load-store buffers and the data-path. Most control functions and data steering operations are based on small memory structures and they are hard to debug. In this paper, we propose a lightweight hardware scheme, called shadow checker to detect faults in these critical units. The entries in these units are tested by means of a shadow entry that mimics intended operation. A mismatch traps an error. The shadow checker shadows an entry for a few thousand cycles before moving on to shadow another. This scheme can be employed to test chips during silicon debug, manufacturing test as well as during regular operation. We ran experiments on 13 SPEC2000 benchmarks and found that our scheme detects 100% of inserted faults.","PeriodicalId":265156,"journal":{"name":"2010 IEEE International Test Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129702339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Post-production performance calibration in analog/RF devices 模拟/射频设备的后期性能校准

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699225

Nathan Kupp, He Huang, P. Drineas, Y. Makris

引用次数: 29

MT-SBST: Self-test optimization in multithreaded multicore architectures MT-SBST:多线程多核架构中的自测优化

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699277

N. Foutris, M. Psarakis, D. Gizopoulos, A. Apostolakis, X. Vera, Antonio González

{"title":"MT-SBST: Self-test optimization in multithreaded multicore architectures","authors":"N. Foutris, M. Psarakis, D. Gizopoulos, A. Apostolakis, X. Vera, Antonio González","doi":"10.1109/TEST.2010.5699277","DOIUrl":"https://doi.org/10.1109/TEST.2010.5699277","url":null,"abstract":"Instruction-based or software-based self-testing (SBST) is a scalable functional testing paradigm that has gained increasing acceptance in testing of single-threaded uniprocessors. Recent computer architecture trends towards chip multiprocessing and multithreading have raised new challenges in the test process. In this paper, we present a novel self-test optimization strategy for multithreaded, multicore microprocessor architectures and apply it to both manufacturing testing (execution from on-chip cache memory) and post-silicon validation (execution from main memory) setups. The proposed self-test program execution optimization aims to: (a) take maximum advantage of the available execution parallelism provided by multiple threads and multiple cores, (b) preserve the high fault coverage that single-thread execution provides for the processor components, and (c) enhance the fault coverage of the thread-specific control logic of the multithreaded multiprocessor. The proposed multithreaded (MT) SBST methodology generates an efficient multithreaded version of the test program and schedules the resulting test threads into the hardware threads of the processor to reduce the overall test execution time and on the same time to increase the overall fault coverage. We demonstrate our methodology in the OpenSPARC T1 processor model which integrates eight CPU cores, each one supporting four hardware threads. MT-SBST methodology and scheduling algorithm significantly speeds up self-test time at both the core level (3.6 times) and the processor level (6.0 times) against single-threaded execution, while at the same time it improves the overall fault coverage. Compared with straightforward multithreaded execution, it reduces the self-test time at both the core level and the processor level by 33% and 20%, respectively. Overall, MT-SBST reaches more than 91% stuck-at fault coverage for the functional units and 88% for the entire chip multiprocessor, a total of more than 1.5M logic gates.","PeriodicalId":265156,"journal":{"name":"2010 IEEE International Test Conference","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128761908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 29

A programmable BIST for DRAM testing and diagnosis 用于DRAM测试和诊断的可编程BIST

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699247

P. Bernardi, M. Grosso, M. Reorda, Y. Zhang

引用次数: 26

System reliability evaluation using concurrent multi-level simulation of structural faults 基于并行多级结构故障模拟的系统可靠性评估

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699309

M. Kochte, Christian G. Zoellin, R. Baranowski, M. Imhof, H. Wunderlich, N. Hatami, S. Carlo, P. Prinetto

引用次数: 5

QED: Quick Error Detection tests for effective post-silicon validation QED:快速错误检测测试，用于有效的硅后验证

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699215

Ted Hong, Yanjing Li, Sung-Boem Park, Diana Mui, David C. Lin, Ziyad Abdel Kaleq, N. Hakim, Helia Naeimi, Donald S. Gardner, S. Mitra

{"title":"QED: Quick Error Detection tests for effective post-silicon validation","authors":"Ted Hong, Yanjing Li, Sung-Boem Park, Diana Mui, David C. Lin, Ziyad Abdel Kaleq, N. Hakim, Helia Naeimi, Donald S. Gardner, S. Mitra","doi":"10.1109/TEST.2010.5699215","DOIUrl":"https://doi.org/10.1109/TEST.2010.5699215","url":null,"abstract":"Long error detection latency, the time elapsed between the occurrence of an error caused by a bug and its manifestation as a system-level failure, is a major challenge in post-silicon validation of robust systems. In this paper, we present a new technique called Quick Error Detection (QED), which transforms existing post-silicon validation tests into new validation tests that significantly reduce error detection latency. QED transformations allow flexible tradeoffs between error detection latency, coverage, and complexity, and can be implemented in software with little or no hardware changes. Results obtained from hardware experiments on quad-core Intel® Core™ i7 hardware platforms and from simulations on a multi-core MIPS processor design demonstrate that: 1. QED significantly improves error detection latencies by six orders of magnitude, i.e., from billions of cycles to a few thousand cycles or less. 2. QED transformations do not degrade the coverage of validation tests as estimated empirically by measuring the maximum operating frequencies over a wide range of operating voltage points. 3. QED tests improve coverage by detecting errors that escape the original non-QED tests.","PeriodicalId":265156,"journal":{"name":"2010 IEEE International Test Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125382031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 85