2010 IEEE International Test Conference最新文献_第7页

Principal Component Analysis-based compensation for measurement errors due to mechanical misalignments in PCB testing 基于主成分分析的PCB测量误差补偿方法

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699249

Xin He, Y. Malaiya, A. Jayasumana, K. Parker, S. Hird

{"title":"Principal Component Analysis-based compensation for measurement errors due to mechanical misalignments in PCB testing","authors":"Xin He, Y. Malaiya, A. Jayasumana, K. Parker, S. Hird","doi":"10.1109/TEST.2010.5699249","DOIUrl":"https://doi.org/10.1109/TEST.2010.5699249","url":null,"abstract":"Capacitive Leadframe Testing is capable of detecting open solder defects in Printed Circuit Boards (PCB). Principal Component Analysis (PCA)-based approach has been shown to be effective in identifying outlier devices using Capacitive Leadframe Testing measurements. In practice, when a sense plate orientation is shifted or tilted, the resulting measurement variation makes detecting outliers harder. Approaches are introduced to compensate for the ‘abnormal’ measurements due to sense-plate variations. A PCA based technique is developed to estimate the relative amount of tilt and shift in sense plates. Such estimates can be used to compensate for mechanical misalignments. It can also isolate the misalignment related information from the defect related information in the data. The effectiveness of this technique in the presence of the two common forms of mechanical variations is illustrated using experimental measurements from a laboratory setting. The approach is not sensitive to the order of pins, and as such, shows promise for detection of complex but systematic errors introduced by sense plate misalignments.","PeriodicalId":265156,"journal":{"name":"2010 IEEE International Test Conference","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126177899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Low power compression of incompatible test cubes 不兼容测试立方体的低功耗压缩

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699274

Dariusz Czysz, Grzegorz Mrugalski, N. Mukherjee, J. Rajski, Przemyslaw Szczerbicki, J. Tyszer

引用次数: 18

A diagnostic test generation system 诊断测试生成系统

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699237

Yu Zhang, V. Agrawal

引用次数: 52

A MEMS based device interface board 基于MEMS的器件接口板

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699296

Nabeeh Kandalaft, I. Basith, R. Rashidzadeh

引用次数: 7

Precision audio nulling instrumentation achieves near −140dB measurements in a production environment 精密音频零化仪器在生产环境中实现近- 140dB的测量

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699262

Carl Karandjeff, Chris Hannaford

引用次数: 1

Low-cost quality assurance techniques for high-performance mixed-signal/RF circuits and systems 用于高性能混合信号/射频电路和系统的低成本质量保证技术

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699287

Hsiu-Ming Chang, K. Cheng

{"title":"Low-cost quality assurance techniques for high-performance mixed-signal/RF circuits and systems","authors":"Hsiu-Ming Chang, K. Cheng","doi":"10.1109/TEST.2010.5699287","DOIUrl":"https://doi.org/10.1109/TEST.2010.5699287","url":null,"abstract":"There exist a variety of quality assurance techniques for tasks ranging from post-silicon validation, silicon debugging, manufacturing testing, in-field testing, and life time resiliency. Adding dedicated circuitry to exclusively support each task would be too costly, as each technique incurs non-trivial overheads. This paper describes three cost-effective quality assurance techniques that attempt to increase the reuse and sharing of test circuitry for multiple quality assurance tasks. First, we propose to reuse the calibration circuitry in mixed-signal/RF systems for manufacturing testing. Then, we propose the concept of application-aware testing for which application-specific criteria are used for defect screening of components. Some of the manufacturing defects which do not cause any system failures for the target applications will not be rejected and thus resulting in yield enhancement. We also develop an all-digital built-in self-test technique for mixed-signal and RF circuits that can be further used to tune the circuit performance. These techniques are demonstrated using digitally-assisted analog circuits and three-dimensional (3D) integrated designs.","PeriodicalId":265156,"journal":{"name":"2010 IEEE International Test Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130519997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Robust algorithms for high quality Test Pattern Generation using Boolean Satisfiability 基于布尔可满足性的高质量测试模式生成鲁棒算法

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699289

Stephan Eggersgluss, R. Drechsler

{"title":"Robust algorithms for high quality Test Pattern Generation using Boolean Satisfiability","authors":"Stephan Eggersgluss, R. Drechsler","doi":"10.1109/TEST.2010.5699289","DOIUrl":"https://doi.org/10.1109/TEST.2010.5699289","url":null,"abstract":"Algorithms for Automatic Test Pattern Generation (ATPG) have to provide a high fault coverage in order to satisfy the quality demands of the chip industry. However, classical structural ATPG algorithms have problems to cope with the increased complexity of modern chip designs. The number of faults for which no test can be generated grows and the demands of the industry are compromised. New algorithms are necessary to retain the quality level. This results in a renewed interest in efficient ATPG algorithms which are fast and robust. ATPG algorithms based on Boolean Satisfiability (SAT) are a promising alternative to structural algorithms being very robust. However, SAT-based ATPG suffers from several limitations such as high run time or over-specified tests which prevent the use in industrial application. This paper proposes a SAT-based ATPG framework, which overcomes the limitations and allows for an efficient application in industrial practice. The framework is able to handle tri-state elements as well as unknown states. SAT formulations for the most prevalent fault models are proposed with special attention paid on the generation of high-quality tests. Novel techniques are introduced which boost the performance of the SAT-based ATPG process and reduce the number of unclassified faults to a minimum. Experimental results on large industrial circuits with multi-million elements show a significantly increased fault efficiency and very high fault coverage. The techniques presented make SAT-based ATPG suitable for the complexity of future designs and new complex fault models.","PeriodicalId":265156,"journal":{"name":"2010 IEEE International Test Conference","volume":"192 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121467990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

Improving fault diagnosis accuracy by automatic test set modification 通过自动修改测试集，提高故障诊断的准确性

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699250

Luca Amati, C. Bolchini, F. Salice, F. Franzoso

引用次数: 8

Error-locality-aware linear coding to correct multi-bit upsets in SRAMs 错误位置感知线性编码以纠正sram中的多位扰动

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699220

S. Shamshiri, K. Cheng

引用次数: 36

Scan chain securization though Open-Circuit Deadlocks 基于开路死锁的扫描链安全

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699300

M. Portolan, B. G. V. Treuren, Suresh Goyal

引用次数: 0