Robust algorithms for high quality Test Pattern Generation using Boolean Satisfiability

Abstract

Algorithms for Automatic Test Pattern Generation (ATPG) have to provide a high fault coverage in order to satisfy the quality demands of the chip industry. However, classical structural ATPG algorithms have problems to cope with the increased complexity of modern chip designs. The number of faults for which no test can be generated grows and the demands of the industry are compromised. New algorithms are necessary to retain the quality level. This results in a renewed interest in efficient ATPG algorithms which are fast and robust. ATPG algorithms based on Boolean Satisfiability (SAT) are a promising alternative to structural algorithms being very robust. However, SAT-based ATPG suffers from several limitations such as high run time or over-specified tests which prevent the use in industrial application. This paper proposes a SAT-based ATPG framework, which overcomes the limitations and allows for an efficient application in industrial practice. The framework is able to handle tri-state elements as well as unknown states. SAT formulations for the most prevalent fault models are proposed with special attention paid on the generation of high-quality tests. Novel techniques are introduced which boost the performance of the SAT-based ATPG process and reduce the number of unclassified faults to a minimum. Experimental results on large industrial circuits with multi-million elements show a significantly increased fault efficiency and very high fault coverage. The techniques presented make SAT-based ATPG suitable for the complexity of future designs and new complex fault models.