{"title":"Increasing PRPG-based compression by delayed justification","authors":"P. Wohl, J. Waicukauski, T. Finklea","doi":"10.1109/TEST.2010.5699226","DOIUrl":"https://doi.org/10.1109/TEST.2010.5699226","url":null,"abstract":"Scan testing and scan compression have become key components for reducing test cost, and most high-compression schemes are based on linear, sequential compressors e.g., pseudo-random pattern generators (PRPG). We present a novel technique to increase PRPG-based compression by modifying test generation so that justification of certain decision nodes is delayed and merged with PRPG seed computation. Our method does not affect test coverage or diagnosis, requires no hardware support, and can be applied to any linear compression scheme. Results on industrial designs demonstrate consistent increase in compression.","PeriodicalId":265156,"journal":{"name":"2010 IEEE International Test Conference","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129886127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Mahmut Yilmaz, Baosheng Wang, Jayalakshmi Rajaraman, Tom Olsen, K. Sobti, D. Elvey, J. Fitzgerald, G. Giles, Weiyu Chen
{"title":"The scan-DFT features of AMD's next-generation microprocessor core","authors":"Mahmut Yilmaz, Baosheng Wang, Jayalakshmi Rajaraman, Tom Olsen, K. Sobti, D. Elvey, J. Fitzgerald, G. Giles, Weiyu Chen","doi":"10.1109/TEST.2010.5699203","DOIUrl":"https://doi.org/10.1109/TEST.2010.5699203","url":null,"abstract":"There is an ever-increasing demand for higher performance microprocessors within a given power budget. This demand forces design choices - that were once seen only in high-speed custom blocks - to spread throughout the microprocessor core. These unique design structures, combined with the nanometer technology test challenges such as crosstalk, process variations, power-supply noise, and resistive short and open defects, lead to unique test challenges for today's high-performance microprocessor core. In this paper, we present the scan architecture-related design-for-test (DFT) features and corresponding verification strategies of the nextgeneration Advanced Micro Devices (AMD) high-performance microprocessor core.","PeriodicalId":265156,"journal":{"name":"2010 IEEE International Test Conference","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115298773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"High-Volume Scan Analysis: Practical challenges and applications for industrial IC development","authors":"D. Carder, Steve Palosh, R. Raina","doi":"10.1109/TEST.2010.5699286","DOIUrl":"https://doi.org/10.1109/TEST.2010.5699286","url":null,"abstract":"This paper describes the challenges faced with the deployment of a High-Volume Scan Diagnostic Analysis flow that spans multiple knowledge domains from IC design to the production floor. Despite the challenges, the paper also reports successes in the areas of Scan Test cleanup, Yield improvement, Correlation of failure modes across multiple devices, and tie-in with pre-identified Lithography hotspots. In closing, the paper discusses open challenges that require collaboration from several stakeholders in semiconductor industry.","PeriodicalId":265156,"journal":{"name":"2010 IEEE International Test Conference","volume":"111 3S 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126078411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Tran, A. Virazel, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, H. Wunderlich
{"title":"Parity prediction synthesis for nano-electronic gate designs","authors":"D. Tran, A. Virazel, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, H. Wunderlich","doi":"10.1109/TEST.2010.5699312","DOIUrl":"https://doi.org/10.1109/TEST.2010.5699312","url":null,"abstract":"In this paper we investigate the possibility of using commercial synthesis tools to build parity predictors for nano-electronic gates designs. They will be used as redundant resources for robustness improvement for future CMOS technology nodes.","PeriodicalId":265156,"journal":{"name":"2010 IEEE International Test Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125314109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Predictive analysis for projecting test compression levels","authors":"O. Sinanoglu, S. Almukhaizim","doi":"10.1109/TEST.2010.5699228","DOIUrl":"https://doi.org/10.1109/TEST.2010.5699228","url":null,"abstract":"Test data compression is widely employed in scan designs to tackle high test data volume and test time problems. Given the number of scan-in pins available in the ATE, architectural decisions regarding the number of internal scan chains directly impact the compression level attained. While targeting an aggressive compression level by increasing the number of internal scan chains would reduce the test data volume per encodable pattern, the cost of applying more patterns serially, to restore the coverage loss, offsets the compression benefits. Therefore, a predictive analysis is necessary to determine the best possible compression configuration, enabling the designers to make DfT architectural decisions early on in the design cycle to minimize test costs. In this paper, we propose a suite of predictive techniques geared towards projecting test cost for any given compression-based scan configuration. The appropriate technique is selected by designers based on which stage the design is in, the design abstraction and the amount of information available, the permissible computational complexity of the techniques, and the accuracy of the projected optimal compression ratio.","PeriodicalId":265156,"journal":{"name":"2010 IEEE International Test Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114922420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Janine Chen, B. Bolin, Li-C. Wang, Jing Zeng, D. Drmanac, Michael Mateja
{"title":"Mining AC delay measurements for understanding speed-limiting paths","authors":"Janine Chen, B. Bolin, Li-C. Wang, Jing Zeng, D. Drmanac, Michael Mateja","doi":"10.1109/TEST.2010.5699258","DOIUrl":"https://doi.org/10.1109/TEST.2010.5699258","url":null,"abstract":"Speed-limiting paths are critical paths that limit the performance of one or more silicon chips. This paper present a data mining methodology for analyzing speed-limiting paths extracted from AC delay test measurements. Based on data collected on 15 packaged silicon units of a four-core microprocessor design, we show that the proposed methodology can efficiently discovered actionable, design-related knowledge that would be difficult to find otherwise.","PeriodicalId":265156,"journal":{"name":"2010 IEEE International Test Conference","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115052942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Surviving state disruptions caused by test: The “Lobotomy Problem”","authors":"K. Parker","doi":"10.1109/TEST.2010.5699260","DOIUrl":"https://doi.org/10.1109/TEST.2010.5699260","url":null,"abstract":"The practice of initializing a board or system for testing purposes is not an exact science, but rather, pursued empirically and with little help from IC designers. This paper examines some of the issues and trends that justify adding features to IEEE 1149.1 that will facilitate safe, fast and effective initialization of a board or system, to get it ready for testing and to leave it in a safe state upon completion of testing.","PeriodicalId":265156,"journal":{"name":"2010 IEEE International Test Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129762916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A roaming memory test bench for detecting particle induced SEUs","authors":"J. Gallière, P. Rech, P. Girard, L. Dilillo","doi":"10.1109/TEST.2010.5699302","DOIUrl":"https://doi.org/10.1109/TEST.2010.5699302","url":null,"abstract":"In this paper, we propose a memory based test bench able to record soft errors that may occur to modern circuits in a certain environment. This system allows a good flexibility from different points of view. It is conceived to be modular, programmable, low power consuming and portable. Consequently, it can operate in various experimental conditions such as under artificial sources of particles as well as in natural ambience, from the earth surface to spatial environment.","PeriodicalId":265156,"journal":{"name":"2010 IEEE International Test Conference","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124244499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Systematic defect identification through layout snippet clustering","authors":"W. Tam, O. Poku, Shawn Blanton","doi":"10.1109/TEST.2010.5699239","DOIUrl":"https://doi.org/10.1109/TEST.2010.5699239","url":null,"abstract":"Systematic defects due to design-process interactions are a dominant component of integrated circuit (IC) yield loss in nano-scaled technologies. Test structures do not adequately represent the product in terms of feature diversity and feature volume, and therefore are unable to identify all the systematic defects that affect the product. This paper describes a method that uses diagnosis to identify layout features that do not yield as expected. Specifically, clustering techniques are applied to layout snippets of diagnosis-implicated regions from (ideally) a statistically-significant number of IC failures for identifying feature commonalties. Experiments involving an industrial chip demonstrate the identification of possible systematic yield loss due to lithographic hotspots.","PeriodicalId":265156,"journal":{"name":"2010 IEEE International Test Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114216677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Zhaobo Zhang, Zhanglei Wang, Xinli Gu, K. Chakrabarty
{"title":"Board-level fault diagnosis using an error-flow dictionary","authors":"Zhaobo Zhang, Zhanglei Wang, Xinli Gu, K. Chakrabarty","doi":"10.1109/TEST.2010.5699251","DOIUrl":"https://doi.org/10.1109/TEST.2010.5699251","url":null,"abstract":"Diagnosis of functional failures is critical for locating manufacturing defects, increasing yield, and reducing field returns. It is important to narrow down the defective module in a failed component during board-level diagnosis. In this paper, a generic fault-diagnosis method based on an error-flow dictionary is presented to identify the root cause of functional failures on a chip or board. Error propagation mimics actual dataflow in a circuit, thus it reflects the native (functional) mode of circuit operation. In contrast to conventional fault syndromes, error flow includes the failure information in terms of circuit functionality, which significantly facilitates the diagnosis of functional failures. In the proposed diagnosis procedure, error flow is first learned from a good circuit by intentionally inserting faults, and then the root cause of a failing circuit is determined by comparing the similarity between the pre-learned error flow and the error flow observed from the failing circuit. The similarity of two error flows is evaluated based on the length of the longest common subsequence in string matching. Results for an open-source RISC SoC and an industrial communication circuit highlight the effectiveness of the proposed method.","PeriodicalId":265156,"journal":{"name":"2010 IEEE International Test Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114360928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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