2010 IEEE International Test Conference最新文献_第2页

An on-line monitoring technique for electrode degradation in bio-fluidic microsystems 生物流体微系统中电极降解的在线监测技术

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699269

Qais Al-Gayem, Hongyuan Liu, A. Richardson, N. Burd, M. Kumar

引用次数: 9

Dynamic channel allocation for higher EDT compression in SoC designs 动态信道分配在SoC设计中实现更高的EDT压缩

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699227

M. Kassab, Grzegorz Mrugalski, N. Mukherjee, J. Rajski, Jakub Janicki, J. Tyszer

引用次数: 18

Case study of scan chain diagnosis and PFA on a low yield wafer 低收率晶圆片扫描链诊断与PFA的案例研究

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699310

Yu Huang, B. Benware, Wu-Tung Cheng, Ting-Pu Tai, F. Kuo, Yuan-Shih Chen

引用次数: 0

AXIe® 2.0 and MVP-C: Open ATE software standards AXIe®2.0和MVP-C:开放式ATE软件标准

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699294

Kenneth Spargo

引用次数: 0

Mask versus Schematic - an enhanced design-verification flow for first silicon success 掩模与原理图-第一个硅成功的增强设计验证流程

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699238

T. Luo, Eric Leong, M. Chao, P. Fisher, Wen-Hsiang Chang

{"title":"Mask versus Schematic - an enhanced design-verification flow for first silicon success","authors":"T. Luo, Eric Leong, M. Chao, P. Fisher, Wen-Hsiang Chang","doi":"10.1109/TEST.2010.5699238","DOIUrl":"https://doi.org/10.1109/TEST.2010.5699238","url":null,"abstract":"Layout versus Schematic (LVS) is a commonly used technique employed at the design stage to insure the correctness of physical layout. However, as process technologies continually advance, increasingly complex boolean operations are required to produce the desired on-mask patterns, which are frequently optimized to enhance transistor performance and process margin. Design layout which has been verified by LVS may undergo substantial layout changes when subjected to the mask generation booleans, with potential implications for performance and margin estimation, particularly given the aggressive use of stressors in modern CMOS technologies. Errors in mask generation booleans, which are very difficult to detect by present primitive inspection methods, can easily result in functional failure although the initial LVS predicted success. Therefore, LVS performed at the design stage is no longer an iron-clad guarantee of chip functionality in advanced process technologies. In this paper, we introduce Mask-versus-Schematic (MVS) verification, a novel design verification flow which directly compares the schematic netlist with a netlist extracted after application of all mask generation booleans, in order to insure the correctness of the final mask data just before tapeout. Furthermore, the introduced methodology can be performed using currently available physical verification EDA tools. The experimental results presented here, using examples from some of the industry's most advanced process technology nodes, demonstrate the effectiveness and efficiency of this methodology in detecting errors resulting from mask generation boolean operations.","PeriodicalId":265156,"journal":{"name":"2010 IEEE International Test Conference","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116326982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Vendor-agnostic native compression engine 与供应商无关的本机压缩引擎

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699311

Vance Threatt, Atchyuth Gorti, J. Rearick, Shaishav Parikh, Anirudh Kadiyala, Aditya Jagirdar, Andy Halliday

引用次数: 0

Rapid FPGA delay characterization using clock synthesis and sparse sampling 使用时钟合成和稀疏采样的快速FPGA延迟表征

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699248

Mehrdad Majzoobi, Eva L. Dyer, Ahmed Elnably, F. Koushanfar

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引用次数: 29

A new method for estimating spectral performance of ADC from INL 一种利用INL估计ADC频谱性能的新方法

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699273

Jingbo Duan, Le Jin, Degang Chen

引用次数: 5

Redundant core testing on the cell BE microprocessor cell BE微处理器的冗余核心测试

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699206

David Iverson, Dan Dickinson, John Masson, Christina Newman-LaBounty, Daniel Simmons, William Tanona

引用次数: 6

Methodology for early and accurate test power estimation at RTL 在RTL进行早期和准确的测试功率估计的方法

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699305

Abhay Singh, M. Shetty, S. Ravi, Ravindra Nibandhe

引用次数: 2