挖掘交流延迟测量来理解限速路径

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI:10.1109/TEST.2010.5699258

Janine Chen, B. Bolin, Li-C. Wang, Jing Zeng, D. Drmanac, Michael Mateja

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引用次数: 14

摘要

限速路径是限制一个或多个硅芯片性能的关键路径。本文提出了一种数据挖掘方法，用于分析从交流延迟测试测量中提取的限速路径。基于对一个四核微处理器设计的15个封装硅单元收集的数据，我们表明，所提出的方法可以有效地发现可操作的、与设计相关的知识，否则很难找到。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Mining AC delay measurements for understanding speed-limiting paths

Speed-limiting paths are critical paths that limit the performance of one or more silicon chips. This paper present a data mining methodology for analyzing speed-limiting paths extracted from AC delay test measurements. Based on data collected on 15 packaged silicon units of a four-core microprocessor design, we show that the proposed methodology can efficiently discovered actionable, design-related knowledge that would be difficult to find otherwise.

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2010 IEEE International Test Conference

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