High-Volume Scan Analysis: Practical challenges and applications for industrial IC development

Abstract

This paper describes the challenges faced with the deployment of a High-Volume Scan Diagnostic Analysis flow that spans multiple knowledge domains from IC design to the production floor. Despite the challenges, the paper also reports successes in the areas of Scan Test cleanup, Yield improvement, Correlation of failure modes across multiple devices, and tie-in with pre-identified Lithography hotspots. In closing, the paper discusses open challenges that require collaboration from several stakeholders in semiconductor industry.