Mahmut Yilmaz, Baosheng Wang, Jayalakshmi Rajaraman, Tom Olsen, K. Sobti, D. Elvey, J. Fitzgerald, G. Giles, Weiyu Chen
{"title":"The scan-DFT features of AMD's next-generation microprocessor core","authors":"Mahmut Yilmaz, Baosheng Wang, Jayalakshmi Rajaraman, Tom Olsen, K. Sobti, D. Elvey, J. Fitzgerald, G. Giles, Weiyu Chen","doi":"10.1109/TEST.2010.5699203","DOIUrl":null,"url":null,"abstract":"There is an ever-increasing demand for higher performance microprocessors within a given power budget. This demand forces design choices - that were once seen only in high-speed custom blocks - to spread throughout the microprocessor core. These unique design structures, combined with the nanometer technology test challenges such as crosstalk, process variations, power-supply noise, and resistive short and open defects, lead to unique test challenges for today's high-performance microprocessor core. In this paper, we present the scan architecture-related design-for-test (DFT) features and corresponding verification strategies of the nextgeneration Advanced Micro Devices (AMD) high-performance microprocessor core.","PeriodicalId":265156,"journal":{"name":"2010 IEEE International Test Conference","volume":"54 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 IEEE International Test Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TEST.2010.5699203","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 12
Abstract
There is an ever-increasing demand for higher performance microprocessors within a given power budget. This demand forces design choices - that were once seen only in high-speed custom blocks - to spread throughout the microprocessor core. These unique design structures, combined with the nanometer technology test challenges such as crosstalk, process variations, power-supply noise, and resistive short and open defects, lead to unique test challenges for today's high-performance microprocessor core. In this paper, we present the scan architecture-related design-for-test (DFT) features and corresponding verification strategies of the nextgeneration Advanced Micro Devices (AMD) high-performance microprocessor core.