AMD下一代微处理器核心的扫描- dft功能

Mahmut Yilmaz, Baosheng Wang, Jayalakshmi Rajaraman, Tom Olsen, K. Sobti, D. Elvey, J. Fitzgerald, G. Giles, Weiyu Chen
{"title":"AMD下一代微处理器核心的扫描- dft功能","authors":"Mahmut Yilmaz, Baosheng Wang, Jayalakshmi Rajaraman, Tom Olsen, K. Sobti, D. Elvey, J. Fitzgerald, G. Giles, Weiyu Chen","doi":"10.1109/TEST.2010.5699203","DOIUrl":null,"url":null,"abstract":"There is an ever-increasing demand for higher performance microprocessors within a given power budget. This demand forces design choices - that were once seen only in high-speed custom blocks - to spread throughout the microprocessor core. These unique design structures, combined with the nanometer technology test challenges such as crosstalk, process variations, power-supply noise, and resistive short and open defects, lead to unique test challenges for today's high-performance microprocessor core. In this paper, we present the scan architecture-related design-for-test (DFT) features and corresponding verification strategies of the nextgeneration Advanced Micro Devices (AMD) high-performance microprocessor core.","PeriodicalId":265156,"journal":{"name":"2010 IEEE International Test Conference","volume":"54 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":"{\"title\":\"The scan-DFT features of AMD's next-generation microprocessor core\",\"authors\":\"Mahmut Yilmaz, Baosheng Wang, Jayalakshmi Rajaraman, Tom Olsen, K. Sobti, D. Elvey, J. Fitzgerald, G. Giles, Weiyu Chen\",\"doi\":\"10.1109/TEST.2010.5699203\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"There is an ever-increasing demand for higher performance microprocessors within a given power budget. This demand forces design choices - that were once seen only in high-speed custom blocks - to spread throughout the microprocessor core. These unique design structures, combined with the nanometer technology test challenges such as crosstalk, process variations, power-supply noise, and resistive short and open defects, lead to unique test challenges for today's high-performance microprocessor core. In this paper, we present the scan architecture-related design-for-test (DFT) features and corresponding verification strategies of the nextgeneration Advanced Micro Devices (AMD) high-performance microprocessor core.\",\"PeriodicalId\":265156,\"journal\":{\"name\":\"2010 IEEE International Test Conference\",\"volume\":\"54 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"12\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 IEEE International Test Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/TEST.2010.5699203\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 IEEE International Test Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TEST.2010.5699203","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 12

摘要

在给定的功率预算内,对高性能微处理器的需求不断增加。这种需求迫使设计选择——曾经只在高速定制模块中看到——扩散到整个微处理器核心。这些独特的设计结构,再加上纳米技术的测试挑战,如串扰、工艺变化、电源噪声、电阻性短路和开放缺陷,为当今的高性能微处理器核心带来了独特的测试挑战。在本文中,我们提出了扫描架构相关的测试设计(DFT)特征和相应的验证策略的下一代高级微设备(AMD)高性能微处理器核心。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
The scan-DFT features of AMD's next-generation microprocessor core
There is an ever-increasing demand for higher performance microprocessors within a given power budget. This demand forces design choices - that were once seen only in high-speed custom blocks - to spread throughout the microprocessor core. These unique design structures, combined with the nanometer technology test challenges such as crosstalk, process variations, power-supply noise, and resistive short and open defects, lead to unique test challenges for today's high-performance microprocessor core. In this paper, we present the scan architecture-related design-for-test (DFT) features and corresponding verification strategies of the nextgeneration Advanced Micro Devices (AMD) high-performance microprocessor core.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信