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BIST of I/O circuit parameters via standard boundary scan 通过标准边界扫描的I/O电路参数的BIST
2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699207
S. Sunter, M. Tilmann
{"title":"BIST of I/O circuit parameters via standard boundary scan","authors":"S. Sunter, M. Tilmann","doi":"10.1109/TEST.2010.5699207","DOIUrl":"https://doi.org/10.1109/TEST.2010.5699207","url":null,"abstract":"To minimize test costs for ASICs and boards, many manufacturers use reduced pin-count access and/or boundary scan-based test. Only DC parameters and basic connectivity are tested, because it takes too much engineering effort to test AC performance. This paper describes a BIST circuit that facilitates testing AC performance of I/O pins via standard boundary scan, without modifying or contacting the I/O circuitry. Process-insensitive, RTL-synthesized BIST circuitry is added outside the TAP controller. It uses a system clock and an asynchronous clock generated by a PLL in the IC to control the update and capture timing of the boundary scan cells. Silicon results show that with a typical PLL, I/O delays can be measured with adjustable precision ranging from 5 ns to 50 ps, and measurements can be compared to per-pin test limits on-chip. This permits automated test generation for I/O pin AC (and DC) parameters, and any connected board-level components, and facilitates more multi-site IC testing.","PeriodicalId":265156,"journal":{"name":"2010 IEEE International Test Conference","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117326481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Synthetic DSP approach for novel FPGA-based measurement of error vector magnitude 基于fpga的误差矢量测量的综合DSP方法
2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699224
Devin Morris, W. Eisenstadt, A. Paganini, M. Slamani, Timothy M. Platt, J. Ferrario
{"title":"Synthetic DSP approach for novel FPGA-based measurement of error vector magnitude","authors":"Devin Morris, W. Eisenstadt, A. Paganini, M. Slamani, Timothy M. Platt, J. Ferrario","doi":"10.1109/TEST.2010.5699224","DOIUrl":"https://doi.org/10.1109/TEST.2010.5699224","url":null,"abstract":"A new implementation of EVM measurement has been developed in a production test environment using an FPGA-based DSP processor within an ATE test solution. The focus of interest is in identifying key areas of the DSP that affect measurement quality and optimizing their execution on an FPGA to increase measurement accuracy, precision, repeatability, and reduce test time. This approach defines a real-time processing methodology for signal demodulation and EVM calculation as opposed to traditional PC-based post processing and offline computation of EVM. The analysis of the DSP elements and their corresponding error artifacts are presented in a standard approach to EVM measurement. The experimental results of the digital demodulation system and EVM measurement in MATLAB/Simulink are compared against a bench-top Rohde&Schwarz complex signal generator and vector signal analyzer to qualify the results.","PeriodicalId":265156,"journal":{"name":"2010 IEEE International Test Conference","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121326349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Optimization methods for post-bond die-internal/external testing in 3D stacked ICs 三维堆叠集成电路键合后模内/外测试的优化方法
2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699219
Brandon Noia, K. Chakrabarty, E. Marinissen
{"title":"Optimization methods for post-bond die-internal/external testing in 3D stacked ICs","authors":"Brandon Noia, K. Chakrabarty, E. Marinissen","doi":"10.1109/TEST.2010.5699219","DOIUrl":"https://doi.org/10.1109/TEST.2010.5699219","url":null,"abstract":"Testing of three-dimensional (3D) stacked ICs (SICs) is starting to receive considerable attention in the semiconductor industry. Since the die-stacking steps of thinning, alignment, and bonding can introduce defects, there is a need to test multiple subsequent partial stacks during 3D assembly. We address the problem of test-architecture optimization for 3D stacked ICs to minimize overall test time when either the complete stack only, or the complete stack and multiple partial stacks, need to be tested. We show that optimal test-architecture solutions and test schedules for multiple test insertions are different from their counterparts for a single final stack test. In addition, we present optimization techniques for the testing of TSVs and die-external logic in combination with the dies in the stack.","PeriodicalId":265156,"journal":{"name":"2010 IEEE International Test Conference","volume":"324 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122740511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 66
A high density small size RF test module for high throughput multiple resource testing 用于高吞吐量多资源测试的高密度小尺寸射频测试模块
2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699232
M. Kimishima, S. Mizuno, T. Seki, H. Takeuti, Haruki Nagami, Hideki Shirasu, Y. Haraguti, J. Okayasu, M. Nakanishi
{"title":"A high density small size RF test module for high throughput multiple resource testing","authors":"M. Kimishima, S. Mizuno, T. Seki, H. Takeuti, Haruki Nagami, Hideki Shirasu, Y. Haraguti, J. Okayasu, M. Nakanishi","doi":"10.1109/TEST.2010.5699232","DOIUrl":"https://doi.org/10.1109/TEST.2010.5699232","url":null,"abstract":"This paper describes a drastically downsized RF test module with multiple resources and high throughput for RF ATE systems. The major factor in downsizing is RF circuit technology in the form of RF functional systems in package (RF-SiPs), making it possible to construct RF front-end without both RF cables and RF connectors. Besides the above downsizing, high-speed RF switching operations are also achieved. Consequently, installation of multiple resources and higher throughput for RF testing has been accomplished, resulting in reduced RF test costs.","PeriodicalId":265156,"journal":{"name":"2010 IEEE International Test Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115404370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Low capture power at-speed test in EDT environment EDT环境下低速捕获功率测试
2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699275
Elham K. Moghaddam, J. Rajski, S. Reddy, X. Lin, N. Mukherjee, M. Kassab
{"title":"Low capture power at-speed test in EDT environment","authors":"Elham K. Moghaddam, J. Rajski, S. Reddy, X. Lin, N. Mukherjee, M. Kassab","doi":"10.1109/TEST.2010.5699275","DOIUrl":"https://doi.org/10.1109/TEST.2010.5699275","url":null,"abstract":"This paper presents a novel low capture power test scheme integrated with EDT (Embedded Deterministic Test) environment. The key contribution of this paper is to generate test vectors that in capture mode mimic functional operation from switching activity point of view. Experimental results presented for industrial circuits demonstrate the effectiveness of the proposed method.","PeriodicalId":265156,"journal":{"name":"2010 IEEE International Test Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115415913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Soft error reliability aware placement and routing for FPGAs fpga的软错误可靠性感知放置和路由
2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699279
M. Abdul-Aziz, M. Tahoori
{"title":"Soft error reliability aware placement and routing for FPGAs","authors":"M. Abdul-Aziz, M. Tahoori","doi":"10.1109/TEST.2010.5699279","DOIUrl":"https://doi.org/10.1109/TEST.2010.5699279","url":null,"abstract":"Radiation effects on SRAM-based FPGA configuration memory induce unique failure modes that cannot be found in similar ASIC devices and can translate into permanent errors in the circuit mapped into the FPGA. The physical layout of the mapped circuit has a considerable impact on the overall reliability of the implemented circuit. In this work we present a set of soft error reliability aware placement and routing algorithms, by modifying the original VPR toolset, to improve the reliability of the mapped designs against SEUs occurring in the FPGA SRAM configuration memory. Our proposed approach tries to minimize the number of possible errors in the circuit while optimizing for traditional design constraints, namely, area and delay. Using our approach we were able to reduce the number of total sensitive bits by 58% on average.","PeriodicalId":265156,"journal":{"name":"2010 IEEE International Test Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129627613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
The AB-filling methodology for power-aware at-speed scan testing 用于功率感知高速扫描测试的ab填充方法
2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699299
Tsung-Tang Chen, Po-Han Wu, Kung-Han Chen, J. Rau, Shih-Ming Tzeng
{"title":"The AB-filling methodology for power-aware at-speed scan testing","authors":"Tsung-Tang Chen, Po-Han Wu, Kung-Han Chen, J. Rau, Shih-Ming Tzeng","doi":"10.1109/TEST.2010.5699299","DOIUrl":"https://doi.org/10.1109/TEST.2010.5699299","url":null,"abstract":"ATPG-based technique for reducing shift and capture power during scan testing is presented without any influence on fault coverage. This paper presents Adjacent Backtracing filling (AB-fillingl) which both adjacent and backtracing filling algorithms are used, is integrated in the ATPG algorithm to reduce capture power while feeding the first test pattern into CUT. After our approach for at-speed scan testing, all of test patterns have assigned as partially-specified values with a small number of don't care value (x) bits as in test compression, and it is a low capture power and considering the shift power test pattern. Experimental results for ISCAS'89 benchmark circuits show that the proposed scheme outperforms previous method in capture power.","PeriodicalId":265156,"journal":{"name":"2010 IEEE International Test Conference","volume":"190 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122427540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Multiple fault activation cycle tests for transistor stuck-open faults 晶体管卡开故障的多故障激活循环试验
2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699313
Narendra Devta-Prasanna, A. Gunda, S. Reddy, I. Pomeranz
{"title":"Multiple fault activation cycle tests for transistor stuck-open faults","authors":"Narendra Devta-Prasanna, A. Gunda, S. Reddy, I. Pomeranz","doi":"10.1109/TEST.2010.5699313","DOIUrl":"https://doi.org/10.1109/TEST.2010.5699313","url":null,"abstract":"The usefulness of scan tests with multiple fault activation cycles to improve the coverage of transistor stuck-open faults is investigated. A recent work demonstrated that tests with more than one fault activation cycle can detect additional transition delay faults and inline resistance faults when compared to two-pattern tests applied using the broadside or skewed-load methods. We extend this work to show that such tests can also be used for testing additional transistor stuck-open faults. Experimental results for coverage improvement in several ISCAS-89 benchmark circuits will be discussed.","PeriodicalId":265156,"journal":{"name":"2010 IEEE International Test Conference","volume":"345 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116316890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Practical active compensation techniques for ATE power supply response for testing of mixed signal data storage SOCs 混合信号数据存储soc测试中ATE电源响应的实用有源补偿技术
2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699263
Suri Basharapandiyan, Y. Cai
{"title":"Practical active compensation techniques for ATE power supply response for testing of mixed signal data storage SOCs","authors":"Suri Basharapandiyan, Y. Cai","doi":"10.1109/TEST.2010.5699263","DOIUrl":"https://doi.org/10.1109/TEST.2010.5699263","url":null,"abstract":"We will demonstrate the effectiveness of power supply active compensation techniques in mixed signal device performance testing. Read channel speed sorting for data storage SOCs is used to illustrate how we minimize the power transient effect in ATE test, where read-channel current draw varies drastically between different mission-modes and power-saving-modes. These active compensation ideas are critical when decoupling improvement alone cannot reduce the transients to acceptable levels. Compared to other publications, we are focusing on minimizing large device functionality-induced transients; instead of peak power consumption with ATPG generated tests.","PeriodicalId":265156,"journal":{"name":"2010 IEEE International Test Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115763947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Lessons from at-speed scan deployment on an Intel® Itanium® microprocessor 在Intel®Itanium®微处理器上高速扫描部署的经验教训
2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699256
P. Pant, Joshua Zelman, G. Colón-Bonet, Jennifer Flint, Steve Yurash
{"title":"Lessons from at-speed scan deployment on an Intel® Itanium® microprocessor","authors":"P. Pant, Joshua Zelman, G. Colón-Bonet, Jennifer Flint, Steve Yurash","doi":"10.1109/TEST.2010.5699256","DOIUrl":"https://doi.org/10.1109/TEST.2010.5699256","url":null,"abstract":"Lessons learnt during the deployment of transition scan content on an Intel® Itanium® server microprocessor design and its use for electrical debug and defect screening in high-volume manufacturing are described. While many publications in the area of transition scan show it being practiced as an efficient defect screening tool, only a minority of these designs were high-performance microprocessor designs. This work illustrates the benefits of such techniques on complex microprocessors.","PeriodicalId":265156,"journal":{"name":"2010 IEEE International Test Conference","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124144684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
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