Soft error reliability aware placement and routing for FPGAs

Radiation effects on SRAM-based FPGA configuration memory induce unique failure modes that cannot be found in similar ASIC devices and can translate into permanent errors in the circuit mapped into the FPGA. The physical layout of the mapped circuit has a considerable impact on the overall reliability of the implemented circuit. In this work we present a set of soft error reliability aware placement and routing algorithms, by modifying the original VPR toolset, to improve the reliability of the mapped designs against SEUs occurring in the FPGA SRAM configuration memory. Our proposed approach tries to minimize the number of possible errors in the circuit while optimizing for traditional design constraints, namely, area and delay. Using our approach we were able to reduce the number of total sensitive bits by 58% on average.