2010 IEEE International Test Conference最新文献_第5页

Characterizing mechanical performance of Board Level Interconnects for In-Circuit Test 电路板级互连电路机械性能表征

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699252

Rosa D. Reinosa, A. Allen, E. Benedetto, A. Mcallister

引用次数: 7

On generation of a universal path candidate set containing testable long paths 关于包含可测试长路径的通用路径候选集的生成

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699308

Zijian He, Tao Lv, Huawei Li, Xiaowei Li

引用次数: 1

Leveraging existing power control circuits and power delivery architecture for variability measurement 利用现有的功率控制电路和功率传输架构进行可变性测量

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699268

D. Acharyya, K. Agarwal, J. Plusquellic

{"title":"Leveraging existing power control circuits and power delivery architecture for variability measurement","authors":"D. Acharyya, K. Agarwal, J. Plusquellic","doi":"10.1109/TEST.2010.5699268","DOIUrl":"https://doi.org/10.1109/TEST.2010.5699268","url":null,"abstract":"Embedded test structures are increasingly being used to measure and analyze performance and power variations in product chips to better understand the impact of process variations. In this work, we propose a minimally-invasive, low-overhead technique for characterizing within-die and die-to-die leakage variation. The proposed technique leverages existing power control circuitry added by designers to reduce the power consumption of inactive functional units. We manipulate these ‘sleep islands’ to isolate and measure their leakage current contribution to the chip-wide leakage current. The measured set of sleep island leakage currents reflect the leakage current variation across the chip at a coarse level of resolution. In order to improve resolution, we propose a multiple power supply port (MSP) measurement technique to provide ‘within-island’ leakage current measurements. A calibration technique is described that corrects for differences between the sleep island and MSP approaches, effectively enabling the same information to be obtained using either technique. We demonstrate the techniques on a set of test chips fabricated in 65-nm SOI technology. The results show that leakage current variations across a small test structure array have both a locally random and globally deterministic component that can be accurately mapped using the sleep island or MSP approaches.","PeriodicalId":265156,"journal":{"name":"2010 IEEE International Test Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114965363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A tester architecture suitable for MEMS calibration and testing 一种适合MEMS校准和测试的测试架构

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699298

Lyl M. Ciganda Brasca, P. Bernardi, M. Reorda, D. Barbieri, Maurizio Straiotto, L. Bonaria

引用次数: 7

Clock Gate Test Points 时钟门测试点

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699208

Narendra Devta-Prasanna, A. Gunda

引用次数: 0

Autonomic approaches for enhancing communication QoS in dense Wireless Sensor Networks with real time requirements 具有实时性要求的密集无线传感器网络中增强通信QoS的自主方法

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699288

A. R. Pinto, C. Montez

引用次数: 11

RADPro: Automatic RF analyzer and diagnostic program generation tool RADPro:自动射频分析仪和诊断程序生成工具

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699233

S. Kannan, Bruce C. Kim, G. Srinivasan, F. Taenzler, Richard Antley, Craig Force, F. Mohammed

引用次数: 4

On maximizing the compound yield for 3D Wafer-to-Wafer stacked ICs 关于最大化3D晶圆堆叠ic的化合物良率

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699218

M. Taouil, S. Hamdioui, J. Verbree, E. Marinissen

{"title":"On maximizing the compound yield for 3D Wafer-to-Wafer stacked ICs","authors":"M. Taouil, S. Hamdioui, J. Verbree, E. Marinissen","doi":"10.1109/TEST.2010.5699218","DOIUrl":"https://doi.org/10.1109/TEST.2010.5699218","url":null,"abstract":"Three-Dimensional Stacked IC (3D-SIC) is an emerging technology that provides heterogeneous integration, higher performance, and lower power consumption compared to planar ICs. Fabricating these 3D-SICs using Wafer-to-Wafer (W2W) stacking has several advantages including: high throughput, thin wafer and small die handling, and high TSV density. However, W2W stacking suffers from low compound yield. This paper investigates various matching processes by using different wafer matching criteria in order to maximize the compound yield. It first establishes a framework covering different matching processes and wafer matching criteria for both replenished and non-replenished wafer repositories. Thereafter, a subset of the framework is analyzed. The simulation results show that the compound yield not only depends on the number of stacked dies, die yield, and repository size, but it also strongly depends on the used matching process and the wafer matching criteria. Moreover, by choosing an appropriate wafer matching scenario (e.g., wafer matching process, criterion etc.), the compound yield can be improved up to 13.4% relative to random W2W stacking.","PeriodicalId":265156,"journal":{"name":"2010 IEEE International Test Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130397595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 40

A novel approach to improve test coverage of BSR cells 一种提高BSR细胞检测覆盖率的新方法

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699295

Ankush Srivastava, A. Prajapati, V. Soni

{"title":"A novel approach to improve test coverage of BSR cells","authors":"Ankush Srivastava, A. Prajapati, V. Soni","doi":"10.1109/TEST.2010.5699295","DOIUrl":"https://doi.org/10.1109/TEST.2010.5699295","url":null,"abstract":"In Today's competitive and rapidly changing electronics market, the speed and effectiveness of product testing have a significant impact on time-to-market. You need to make Design-For-Testability (DFT) an essential part of your design process, along with the need for a reliable method of knowing the test coverage and how to improve it. This paper describes the modified Boundary-Scan Register (BSR) Cell, described in IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture, to facilitate the detection of additional manufacturing defects in BSR Cell by adding a small test logic, which will become a part of original BSR Cell. The basic idea is to increase the stuck-at fault coverage of BSR cell by including the update-register (latched parallel output) Flip-Flop in BSR chain and once the update-register is being included in the chain; we can target more manufacturing defects to cover during BSR chain-test. This increases the fault-coverage of the BSR Pad Ring and will also help validation engineers to ease out their debugging efforts on board level with added quality to the delivered chips to customer. This BSR cell design modification can be extended to any of the BC type cell structure, compliant to IEEE Standard 1149.1 Boundary-Scan Architecture.","PeriodicalId":265156,"journal":{"name":"2010 IEEE International Test Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130126307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Test cycle power optimization for scan-based designs 基于扫描设计的测试周期功率优化

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699213

Kun-Han Tsai, Yu Huang, Wu-Tung Cheng, Ting-Pu Tai, A. Kifli

引用次数: 9