2010 IEEE International Test Conference最新文献_第4页

Detecting memory faults in the presence of bit line coupling in SRAM devices 在SRAM器件中位线耦合存在时检测存储器故障

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699246

S. Irobi, Z. Al-Ars, S. Hamdioui

引用次数: 18

Timing skew compensation technique using digital filter with novel linear phase condition 基于新型线性相位条件的数字滤波器时序偏差补偿技术

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699234

Koji Asami, Hiroyuki Miyajima, Tsuyoshi Kurosawa, T. Tateiwa, Haruo Kobayashi

引用次数: 9

Defect-oriented cell-internal testing 面向缺陷的细胞内部测试

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699229

F. Hapke, W. Redemund, J. Schlöffel, Rene Krenz-Baath, Andreas Glowatz, M. Wittke, H. Hashempour, S. Eichenberger

引用次数: 41

Automatic classification of bridge defects 桥梁缺陷自动分类

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699231

J. E. Nelson, W. Tam, R. D. Blanton

引用次数: 19

On techniques for handling soft errors in digital circuits 数字电路软误差处理技术研究

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699278

Warin Sootkaneung, K. Saluja

{"title":"On techniques for handling soft errors in digital circuits","authors":"Warin Sootkaneung, K. Saluja","doi":"10.1109/TEST.2010.5699278","DOIUrl":"https://doi.org/10.1109/TEST.2010.5699278","url":null,"abstract":"Dealing with soft errors due to particle strikes is the next major challenge in implementing digital systems. This study thoroughly investigates the effect of device size on circuit soft error rate and identifies methods to reduce soft error rate in combinational circuits. In particular, we propose three novel methods that upsize only selected gates and /or transistor networks. In order to obtain the most appropriate technique for soft error rate reduction in small technology node circuits, we conduct experiments and compare the results for several upsizing techniques including all gates, selected gates and transistor networks based on their fault sensitivities, and parallel networks with soft error rate saturation consideration. Consequently, it is discovered that some upsizing scenarios perform large improvement whereas others do not or even increase the soft error rate. The use of fault sensitivity analysis approach with parallel transistor network upsizing based on the contribution of each sensitive gate can reasonably reduce overall circuit sensitivity. Experimental results show an average reduction in soft error rate about 20% with a very small area overhead of 2% for benchmark circuits using our technique.","PeriodicalId":265156,"journal":{"name":"2010 IEEE International Test Conference","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124298060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 16

A fast and highly accurate path delay emulation framework for logic-emulation of timing speculation 一种用于时序推测逻辑仿真的快速高精度路径延迟仿真框架

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699267

Shuou Nomura, K. Sankaralingam, Ranganathan Sankaralingam

引用次数: 2

Validating the performance of a 32nm CMOS high speed serial link receiver with adaptive equalization and baud-rate clock data recovery 验证具有自适应均衡和波特率时钟数据恢复功能的32nm CMOS高速串行链路接收器的性能

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699242

S. Puligundla, F. Spagna, Lidong Chen, A. Tran

{"title":"Validating the performance of a 32nm CMOS high speed serial link receiver with adaptive equalization and baud-rate clock data recovery","authors":"S. Puligundla, F. Spagna, Lidong Chen, A. Tran","doi":"10.1109/TEST.2010.5699242","DOIUrl":"https://doi.org/10.1109/TEST.2010.5699242","url":null,"abstract":"On-Die features available for validation and test on an integrated circuit play a major role in evaluating the performance of the functionality being realized by the circuit in a post-silicon environment and can considerably reduce time to market of the end-product. In the case of high-speed IO, it is also important to note that the type of on-die hooks required to debug and validate the performance and robustness of the design depend on several factors, of which the type of I/O architecture chosen plays a key role. In order to support high data rates, the serial I/O design in this paper implements a receiver with adaptive equalization engine for the compensation of inter-symbol interference (ISI) and real-time environmental changes (temperature and voltage). This paper describes the debug hooks and their usage models in such a high-speed I/O designed using a 32nm CMOS process. These hooks have been tested in the lab and proven to be very useful. While the main focus of the paper is to describe the hooks, how they are used in the lab for observing the robustness in the dynamic behavior of the adaptive loops and the measurement results; the reader is also provided with a brief insight into the equations describing the loops behavior together with a description of the loops implementation details.","PeriodicalId":265156,"journal":{"name":"2010 IEEE International Test Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122137063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Modeling the impact of process variation on resistive bridge defects 模拟工艺变化对电阻桥缺陷的影响

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699230

S. Khursheed, Shida Zhong, R. Aitken, B. Al-Hashimi, S. Kundu

引用次数: 12

Structural approach for built-in tests in RF devices 射频器件内建测试的结构方法

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699241

D. Mannath, D. Webster, V. Montaño-Martinez, David Cohen, S. Kush, G. Thiagarajan, A. Sontakke

引用次数: 24

New tools and methodology for advanced parametric and defect structure test 先进的参数化和缺陷结构测试的新工具和方法

2010 IEEE International Test Conference Pub Date : 2010-11-01 DOI: 10.1109/TEST.2010.5699201

R. Robertazzi, L. Medina, E. Shiling, Garry Moore, Ronald Geiger, J. Liao, John Williamson

引用次数: 5