Testing of latch based embedded arrays using scan tests

Abstract

Latch based arrays are commonly used as small embedded memories. There are often a large number of such memories in a design. Due to the large area overhead of memory BISTs, scan is often used to test such memories. In this paper we show that with a minor modification of a marching sequence targeting only the transition delay faults at the latch boundaries, a comprehensive set of faults can be detected. The comprehensive fault set includes all stuck-at, stuck-open and bridging faults inside a cell of the array as well as all inter-cell bridging faults. This test set also includes a retention test for such memories.