A low-cost ATE phase signal generation technique for test applications

Abstract

In this article, an accurate and low-cost clock delay generation system integrated in an automated test equipment (ATE) environment is presented. The input to this system is entirely digital and is driven by a single clock, which can be programmed from the ATE High Speed Digital (HSD) unit. Moreover, the digital input patterns can easily be generated in software off-line; hence, making this system ideal for automated test routines. The system is first discussed and characterized in Matlab under static and dynamic operating conditions. For the static behavior, the impact of the various design tradeoffs on the time resolution is investigated. With regards to the dynamic behavior, the linearity is assessed spectrally with a sinusoidal input and statistically using a Gaussian noise signal. A discrete prototype board is built to validate the correct operation of the system mounted on an ATE to function as a whole. With proper compensation and calibration, a delay resolution of 15 ps was achieved over an 8.4 ns range using a low-speed reference clock running at 16.67 MHz. It is shown through clock scaling that this resolution can improve in direct proportion to increases in the clock frequency.