发布求助
文献互助 智能选刊 最新文献

Proceedings. 'Meeting the Tests of Time'., International Test Conference最新文献

筛选
英文 中文
Cell-based test design method 基于细胞的试验设计方法
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82382
K. Sakashita, T. Hashizume, T. Ohya, I. Takimoto, Shuichi Kato
{"title":"Cell-based test design method","authors":"K. Sakashita, T. Hashizume, T. Ohya, I. Takimoto, Shuichi Kato","doi":"10.1109/TEST.1989.82382","DOIUrl":"https://doi.org/10.1109/TEST.1989.82382","url":null,"abstract":"A cell-based test design method which is consistent with features of cell-based design is introduced. By improving shift register latches, a scan test for asynchronous circuits, as well as delay tests can be executed effectively. Also, by employing a test bus and a selector shift register configuration, a multiple scan-path test is realized attractively, which drastically reduces the execution time of the scan test. This results in the possibility of realizing a hierarchical test design in which the test vectors of module circuits are saved as library data and used in the preparation of the test vector of a newly developed chip and of the schematic and artwork data. It appears that the area overhead and the increase in test time are reasonable for future VLSI chips with the complexity of 1M transistors.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115160927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
High-resolution analog measurement on mixed signal LSI tester 高分辨率模拟测量混合信号LSI测试仪
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82286
Kohei Akiyama, H. Nishimura, K. Anazawa, Akito Kishida, Nobuyuki Kasuga
{"title":"High-resolution analog measurement on mixed signal LSI tester","authors":"Kohei Akiyama, H. Nishimura, K. Anazawa, Akito Kishida, Nobuyuki Kasuga","doi":"10.1109/TEST.1989.82286","DOIUrl":"https://doi.org/10.1109/TEST.1989.82286","url":null,"abstract":"The authors describe the HP 9480, a mixed-signal LSI tester featuring LF source/measurement modules capable of measurements on the order of 100 dB for standard dynamic range, signal-to-noise ratio, or total harmonic distortion measurements. To realize this tester, background noise was minimized by using a unique power supply system and proper ground management, and several function modules were developed. The authors describe the noise reduction techniques and functional modules. Measurement examples are also given.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"127 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123242502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Design-for-testability using test design yield and decision theory 利用测试设计成品率和决策理论进行可测试性设计
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82379
B. Kaminska, Y. Savaria
{"title":"Design-for-testability using test design yield and decision theory","authors":"B. Kaminska, Y. Savaria","doi":"10.1109/TEST.1989.82379","DOIUrl":"https://doi.org/10.1109/TEST.1989.82379","url":null,"abstract":"A framework for prediction and estimation of the test yield and test cost of VLSI systems during the design-for-testability stage is given. As an important extension, the authors present a technique for evaluating the set of possible solutions and selecting the most effective one. This technique is based on the evaluation of test-related performance measures and on decision theory. As a result, a new level of design and test integration is obtained. Experimental results have confirmed the applicability and effectiveness of the method. It is shown that it is possible to derive, in a very straightforward manner, maximum and minimum expected values of the design yields of a strategy (design scheme).<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122886312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Data verification-a prerequisite for heuristic diagnostics 数据验证——启发式诊断的先决条件
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82335
D. Gravel
{"title":"Data verification-a prerequisite for heuristic diagnostics","authors":"D. Gravel","doi":"10.1109/TEST.1989.82335","DOIUrl":"https://doi.org/10.1109/TEST.1989.82335","url":null,"abstract":"The author explains both syntactic and semantic data verification within the context of a test repair loop. He explains how data verification has been used to develop a capability called failure history to learn automatically which defects are the real cause of a given failure. He notes that this can be extended into a heuristic diagnostic capability. However, data verification will continue to be necessary in order to build the empirical knowledge base automatically.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125791350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Composite electro-optical testing of surface-mount device boards-one manufacturer's experience 表面贴装器件板的复合光电测试-一家制造商的经验
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82356
F. J. Langley, Ronald R. Boatright, L. Crosby
{"title":"Composite electro-optical testing of surface-mount device boards-one manufacturer's experience","authors":"F. J. Langley, Ronald R. Boatright, L. Crosby","doi":"10.1109/TEST.1989.82356","DOIUrl":"https://doi.org/10.1109/TEST.1989.82356","url":null,"abstract":"The use of surface-mount devices (SMDs) in the US manufacture of high-quality switchboards presented the need to reduce cost, while maintaining traditional quality and reliability, and without decreasing throughput or adding process steps. Further, the complexity of the display panels demanded a completely automatic test solution without the operator in the loop. The authors describe the use of automatic optical inspection in conjunction with electrical testing for a medium-volume manufacturing situation. The effectiveness of this test solution in meeting the needs of a major change in device technology is quantified from measurement accuracy and consistency viewpoints. Increased production efficiency as compared with previous tests strategies is indicated.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127347198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Experiments on aliasing in signature analysis registers 特征分析寄存器中的混叠实验
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82318
D. Xavier, R. Aitken, A. Ivanov, V. Agarwal
{"title":"Experiments on aliasing in signature analysis registers","authors":"D. Xavier, R. Aitken, A. Ivanov, V. Agarwal","doi":"10.1109/TEST.1989.82318","DOIUrl":"https://doi.org/10.1109/TEST.1989.82318","url":null,"abstract":"An effort is made to validate experimentally predictions on aliasing in signature analysis registers under the independent error model. From the experimental results it appears that the independent error model accurately predicts the probability of aliasing in signature registers. The authors also provide justification for the adoption of a more general asymmetric error model of which the former is a special case; the latter can be used at no extra cost. Among the potential benefits in using the asymmetric error model is the subdivision of faults into classes based on pD and pDbar, the conditional probability, respectively, of the fault-free bit being 1 and the faulty bit being 0 and vice versa, whereby faults in a given class have the same probability of aliasing. Under the independent error model fault classification is based on a single parameter p. Use of an asymmetric model hence provides a better resolution in terms of the classification of faults based on aliasing probability. Experimental results also indicate that considering the asymmetric nature of circuit outputs yields more useful information, especially in the dynamic region of the aliasing curve.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"141 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114851776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A sequential circuit fault simulation by surrogate fault propagation 基于代理故障传播的时序电路故障仿真
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82272
Xaiolin Wang, F. Hill, Zhengkin Mi
{"title":"A sequential circuit fault simulation by surrogate fault propagation","authors":"Xaiolin Wang, F. Hill, Zhengkin Mi","doi":"10.1109/TEST.1989.82272","DOIUrl":"https://doi.org/10.1109/TEST.1989.82272","url":null,"abstract":"A novel technique for synchronous fault simulation of sequential circuits utilizing surrogate fault propagation and backward fault collection is introduced, and its implementation is evaluated. Fault effects which reconverge over time are simulated as exceptions. Evidence which shows SFSSE (synchronous fault simulation by surrogate with exceptions) to be superior to existing approaches is presented. As in deductive and concurrent simulation, execution time drops dramatically as the majority of faults are detected. SFSSE incorporates features of both deductive and parallel fault simulations while avoiding the drawbacks of each of these techniques. In contrast to deductive simulation, fault lists are processed only at primary outputs and memory elements. This is critical with respect to both execution time and storage requirements.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114350977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Fast automatic failbit analysis for DRAMs 快速自动故障位分析的dram
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82326
W. Malzfeldt, W. Mohr, H.-D. Oberle, K. Kodalle
{"title":"Fast automatic failbit analysis for DRAMs","authors":"W. Malzfeldt, W. Mohr, H.-D. Oberle, K. Kodalle","doi":"10.1109/TEST.1989.82326","DOIUrl":"https://doi.org/10.1109/TEST.1989.82326","url":null,"abstract":"Technological failures of DRAMs (dynamic random-access memories) show up in different fault patterns in the failbit map. An automatic program has been developed for testing, fault pattern recognition, classification, and determination of fault class distributions on chips and wafers. The analysis system consists of an ADVANTEST T 3332 memory tester and an ADVANSTAR network with a connection to a remotely located mainframe computer. Selected wafers are tested using the same test conditions as in the production test program in order to reproduce the failbit patterns. The fast automatic failbit analysis was first installed for a 1M DRAM and was later updated for 4M DRAM analysis. Results of the analysis are presented and discussed.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131311638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A testing technique to characterize E/sup 2/PROM's aging and endurance 一种表征E/sup 2/PROM老化和耐久性的测试技术
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82323
M. Lanzoni, P. Olivo, B. Riccò
{"title":"A testing technique to characterize E/sup 2/PROM's aging and endurance","authors":"M. Lanzoni, P. Olivo, B. Riccò","doi":"10.1109/TEST.1989.82323","DOIUrl":"https://doi.org/10.1109/TEST.1989.82323","url":null,"abstract":"The authors present a testing method for monitoring E/sup 2/PROM (electrically erasable programmable ROM) cell aging. The technique is not based on any particular assumption about cell technology: hence it can be used to characterize wearout dynamics in all cases in which charge trapped in tunnel oxide is the main failure mechanism. The method is validated by means of a wide set of measurements performed with automatic test equipment. The characterization can be directed to single cells, thus making it possible to study the main layout dependences of aging phenomena. Possible criticalities of the virgin devices (with respect to supply voltage temperature, etc.) can be determined. A procedure has been developed to extrapolate data obtained with a few programming cycles in order to obtain first-order estimates of the actual device endurance.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"42 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127046469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Prototype testing simplified by scannable buffers and latches 可扫描缓冲器和锁存器简化了原型测试
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82292
A. Halliday, G. Young, A. Crouch
{"title":"Prototype testing simplified by scannable buffers and latches","authors":"A. Halliday, G. Young, A. Crouch","doi":"10.1109/TEST.1989.82292","DOIUrl":"https://doi.org/10.1109/TEST.1989.82292","url":null,"abstract":"Conventional logic devices incorporating boundary scan with the proposed IEEE P1149.1 interface have been shown to offer great improvements in board testing. These improvements are contrasted with traditional approaches for the design verification, debugging, and testing of a prototype system. The incorporation of boundary scan has been demonstrated to impose a minimal real estate overhead and change the process of design verification and testing making it beneficial to both the design engineer and test engineer. The use of devices incorporating boundary scan will reduce the cost of testing. By using the devices that support the P1149.1 architecture in the prototype system considered, some of the problems and questions associated with the verification and testing of prototype systems (or even production systems) were solved. In addition to solving the problems, the verification and testing processes were simplified.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129773925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信