Prototype testing simplified by scannable buffers and latches

Abstract

Conventional logic devices incorporating boundary scan with the proposed IEEE P1149.1 interface have been shown to offer great improvements in board testing. These improvements are contrasted with traditional approaches for the design verification, debugging, and testing of a prototype system. The incorporation of boundary scan has been demonstrated to impose a minimal real estate overhead and change the process of design verification and testing making it beneficial to both the design engineer and test engineer. The use of devices incorporating boundary scan will reduce the cost of testing. By using the devices that support the P1149.1 architecture in the prototype system considered, some of the problems and questions associated with the verification and testing of prototype systems (or even production systems) were solved. In addition to solving the problems, the verification and testing processes were simplified.<>