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Proceedings. 'Meeting the Tests of Time'., International Test Conference最新文献

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The economics of scan design 扫描设计的经济学
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82377
M. Levitt, J. Abraham
{"title":"The economics of scan design","authors":"M. Levitt, J. Abraham","doi":"10.1109/TEST.1989.82377","DOIUrl":"https://doi.org/10.1109/TEST.1989.82377","url":null,"abstract":"The authors present a model that allows the designer to calculate the cost of scan-path design for testability (DFT) for standard cell-based chips. The model is used to estimate the profitability of designs that use DFT techniques over the product life cycle and those that do not. It is shown that, under dynamic market conditions, it is sometimes better to choose a more expensive solution if the product can be delivered faster. Thus, scan-path techniques can more than make up for their extra area if they reduce test generation time and therefore product lead times.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114969985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
High performance electron beam tester for voltage measurement on unpassivated and passivated devices 用于未钝化和钝化器件电压测量的高性能电子束测试仪
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82383
Y. Tokunaga, J. Frosien
{"title":"High performance electron beam tester for voltage measurement on unpassivated and passivated devices","authors":"Y. Tokunaga, J. Frosien","doi":"10.1109/TEST.1989.82383","DOIUrl":"https://doi.org/10.1109/TEST.1989.82383","url":null,"abstract":"An electron-beam tester designated for precise and damage-free voltage measurement and for diagnostics in the interior of highly integrated circuits has been developed. Its specifications meet the requirements necessary for testing present and future generations of integrated circuits with line patterns down to 0.5 mu m. The electron optical column has been optimized for low-energy operation, providing an electron beam of 0.1 mu m diameter with 2 nA current at 1 keV electron energy. The variable extraction voltage system incorporated in the tester not only enables accurate voltage measurements on unpassivated devices, but also offers the possibility of detailed failure analysis on passivated devices. On passivated devices, however, limitations may arise when the passivation layer thickness and the line separation distance reach the same order.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117259822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
An easily computed functional level testability measure 一个易于计算的功能级可测试性度量
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82322
Kurt H. Thearling, J. Abraham
{"title":"An easily computed functional level testability measure","authors":"Kurt H. Thearling, J. Abraham","doi":"10.1109/TEST.1989.82322","DOIUrl":"https://doi.org/10.1109/TEST.1989.82322","url":null,"abstract":"The authors consider the problem of estimating the testability of a digital circuit at the functional level. Using an information-theoretic approach, they have developed a functional testability measure for both controllability and observability. They introduce two techniques that can efficiently and accurately estimate the measure. In addition, some applications of the testability measure for automated design for testability, such as automatic circuit partitioning and test point insertion, are described.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"13 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123298290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 73
Testing conventional logic and memory clusters using boundary scan devices as virtual ATE channels 使用边界扫描设备作为虚拟ATE通道测试传统逻辑和内存集群
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82291
P. Hansen
{"title":"Testing conventional logic and memory clusters using boundary scan devices as virtual ATE channels","authors":"P. Hansen","doi":"10.1109/TEST.1989.82291","DOIUrl":"https://doi.org/10.1109/TEST.1989.82291","url":null,"abstract":"The test of embedded clusters of conventional logic via boundary scan virtual channels has been shown to be a practical way to test and diagnose structural faults where these clusters are inaccessible to standard ATE (automatic test equipment) channels. Huge quantities of data can be created by this technique, which could result in prohibitive storage requirements and poor throughput. By use of topological data compression and special hardware, the storage requirement can be small and test times limited only by the speed of the boundary scan path. After discussing test pattern generation, the boundary scan environment, and the serialization of test patterns and algorithmic patterns, the author presents applications examples.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130362453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
Search strategy switching: an alternative to increased backtracking 搜索策略切换:增加回溯的替代方法
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82369
Hyoung B. Min, W. A. Rogers
{"title":"Search strategy switching: an alternative to increased backtracking","authors":"Hyoung B. Min, W. A. Rogers","doi":"10.1109/TEST.1989.82369","DOIUrl":"https://doi.org/10.1109/TEST.1989.82369","url":null,"abstract":"Test generation algorithms use search strategies to control decision making whenever the algorithms encounter a choice of a signal value or action. The authors' study of traditional search strategies used in automatic test pattern generation (ATPG) has led to the observation that no single strategy is superior for all faults in a circuit or all circuits. Further experimentation led to the conclusion that a combination of search strategies provides better fault coverage and/or faster ATPG for a given backtrack limit. Instead of using just one strategy to the backtrack limit, a primary strategy is used for the first half of the backtrack limit, and then a secondary strategy is used for the second half. The authors present an ATPG cost model based on the number of test generation events. They use this model to explain why search strategy switching is faster and show experimental evidence to verify the search strategy switching theory. The experiments were performed with the ISCAS circuits and the authors' implementation of the FAN algorithm.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114738239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
Hierarchical test pattern generation based on high-level primitives 基于高级原语的分层测试模式生成
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82330
Thomas M. Sarfert, Remo G. Markgraf, E. Trischler, M. Schulz
{"title":"Hierarchical test pattern generation based on high-level primitives","authors":"Thomas M. Sarfert, Remo G. Markgraf, E. Trischler, M. Schulz","doi":"10.1109/TEST.1989.82330","DOIUrl":"https://doi.org/10.1109/TEST.1989.82330","url":null,"abstract":"It is demonstrated that the exploitation of high-level primitives (HLPs) and, in particular, of the knowledge concerning their function in ATPG (automatic test pattern generation) leads to significant improvements in implication, unique sensitization, and multiple backtrace. Motivated by this observation and the necessity of covering all faults inside HLPs, the authors present the extension of the ATPG system SOCRATES to hierarchical test pattern generation, which is based upon HLPs and the strategy of dynamically expanding the HLPs to their gate-level realization, at most one at a time. Experimental results have substantiated that the proposed approach performs significantly better in terms of CPU time, elapsed time, fault coverage, and memory requirements than a gate-level ATPG algorithm. It is expected that the extended SOCRATES algorithm will be capable of coping with circuits consisting of 100000 gates and more within reasonable times, even in a workstation environment.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126452436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 42
Design for testability and test generation for static redundancy system level fault-tolerant circuits 静态冗余系统级容错电路的可测试性和测试生成设计
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82370
C. Stroud, A. Barbour
{"title":"Design for testability and test generation for static redundancy system level fault-tolerant circuits","authors":"C. Stroud, A. Barbour","doi":"10.1109/TEST.1989.82370","DOIUrl":"https://doi.org/10.1109/TEST.1989.82370","url":null,"abstract":"The necessary conditions for designing testable static redundancy system-level fault-tolerant circuits are derived. In addition, algorithms are proposed for the efficient generation of test patterns for fault-tolerant circuits designed to satisfy these testability conditions. The test generation algorithm has been incorporated with an algorithm for the construction of majority voting devices and automated to produce a software package that generates testable fault-tolerant circuits along with test patterns to test the resultant circuit completely. As input, the algorithm requires a testable original circuit, along with an associated set of test patterns and the desired design parameters E, R, and K.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126499912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
A proposed benchmark unit for evaluating electronic troubleshooting expert systems 提出了一种评估电子故障排除专家系统的基准单元
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82280
M. Ben-Bassat, D. Ben-Arie, I. Beniaminy, J. Cheifetz, M. Klinger
{"title":"A proposed benchmark unit for evaluating electronic troubleshooting expert systems","authors":"M. Ben-Bassat, D. Ben-Arie, I. Beniaminy, J. Cheifetz, M. Klinger","doi":"10.1109/TEST.1989.82280","DOIUrl":"https://doi.org/10.1109/TEST.1989.82280","url":null,"abstract":"In order to establish a uniform basis for comparing and evaluating diagnostic expert systems for functional electronic troubleshooting, a real-life benchmark unit is proposed. The HP-3478P unit is essentially identical to the HP-3478A digital multimeter. The authors first outline the criteria that guided them in the selection of this unit from a wide variety of real-life units. They describe the structure of the HP-3478P and its test set. They then provide an illustrative test case and a discussion of the complexity of the unit. The HP-3478P was used to evaluate the AITEST system on a wide variety of cases, and it was found to be very useful.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131032275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A logic analyzer tool that cuts e-beam prober acquisition times 一个逻辑分析工具，减少电子束探头采集时间
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82384
C. G. Talbot, Suresh Rajan
{"title":"A logic analyzer tool that cuts e-beam prober acquisition times","authors":"C. G. Talbot, Suresh Rajan","doi":"10.1109/TEST.1989.82384","DOIUrl":"https://doi.org/10.1109/TEST.1989.82384","url":null,"abstract":"The authors describe a novel tool that dramatically extends the usability of electron-beam probers for long duty cycle applications. The tool is modeled on a conventional logic analyzer (primarily for ease-of-use reasons). The tool comprises both hardware and software, and utilizes new sampling strategies which exploit fully the available detector bandwidth, thereby reducing dramatically typical signal acquisition times. The tool also provides, under certain circumstances, the ability to acquire intermittent signals. The proposed approach improves typical signal acquisition times by two orders of magnitude.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133850466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Clock signal distribution network for high speed testers 高速测试仪时钟信号分配网络
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82295
C. Hsue
{"title":"Clock signal distribution network for high speed testers","authors":"C. Hsue","doi":"10.1109/TEST.1989.82295","DOIUrl":"https://doi.org/10.1109/TEST.1989.82295","url":null,"abstract":"A high-speed clock distribution network is described. By analyzing the transient behavior of the pulse signal along a multisection transmission line, the author develops a new impedance-matching methodology to reduce the internal multireflection processes due to the impedance discontinuities in the signal line. By means of the bisection method, the matched transmission line is converted into a single-input, 2/sup n/-output, binary-tree distribution circuit. The circuit is realized on a planar printed-circuit board. Experimental results show that this distribution system can provide equiamplitude, high-fidelity, nonskewed signals to all the output terminals for pulse signal frequency in excess of 800 MHz.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124445094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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