The economics of scan design

Abstract

The authors present a model that allows the designer to calculate the cost of scan-path design for testability (DFT) for standard cell-based chips. The model is used to estimate the profitability of designs that use DFT techniques over the product life cycle and those that do not. It is shown that, under dynamic market conditions, it is sometimes better to choose a more expensive solution if the product can be delivered faster. Thus, scan-path techniques can more than make up for their extra area if they reduce test generation time and therefore product lead times.<>