发布求助
文献互助 智能选刊 最新文献

Proceedings. 'Meeting the Tests of Time'., International Test Conference最新文献

筛选
英文 中文
Practical considerations in benchmarking digital testing systems 对标数字测试系统的实际考虑
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82403
S. Mourad
{"title":"Practical considerations in benchmarking digital testing systems","authors":"S. Mourad","doi":"10.1109/TEST.1989.82403","DOIUrl":"https://doi.org/10.1109/TEST.1989.82403","url":null,"abstract":"It is noted that there are minimum requirements benchmark circuits have to satisfy in order to be useful in evaluating digital testing systems (DTSs). The circuits need to have a profile that enables the testing to be done in an efficient way. The circuits also need to include commonly used constructs such as bidirectional pins or asynchronous signals. Also, the correctness of different versions of the same circuit needs to be verified in order to make a fair comparison of the different DTSs. The author aims to determine the features that have to be known about the benchmark circuits before using them to evaluate DTSs, to distinguish between the requirements for combinational and sequential circuits, and to show the merit of using a neutral hardware description language to facilitate the transport of the circuits between DTSs.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114618091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Detection of transient faults in microprocessors by concurrent monitoring 微处理器暂态故障的并发监测
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82399
M. Z. Khan, J. Tront
{"title":"Detection of transient faults in microprocessors by concurrent monitoring","authors":"M. Z. Khan, J. Tront","doi":"10.1109/TEST.1989.82399","DOIUrl":"https://doi.org/10.1109/TEST.1989.82399","url":null,"abstract":"Summary form only given. A novel approach, called concurrent processor monitoring for on-line detection of transient faults, that attempts to achieve high error coverage with small error detection latency is proposed. The concept of the execution profile of an instruction is defined and is used for detecting control flow and execution errors. To implement this scheme, a watchdog processor is designed for monitoring operation of the main processor. The effectiveness of this technique is demonstrated through computer simulations. Simulation studies on an 8086-based system indicate a fault coverage of 97% and a very small fault latency time. The hardware overhead for the watchdog processor is about 28%. By use of the basic design concept, test hardware could be implemented directly on the microprocessor chip and the hardware cost would be further reduced.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114938904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Testability expertise and test planning from high-level specifications 可测试性专业知识和高级规格的测试计划
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82357
M. Paulet, M. Karam, G. Saucier
{"title":"Testability expertise and test planning from high-level specifications","authors":"M. Paulet, M. Karam, G. Saucier","doi":"10.1109/TEST.1989.82357","DOIUrl":"https://doi.org/10.1109/TEST.1989.82357","url":null,"abstract":"The testability expertise of boards and ASICs (application-specific integrated circuits) relies on high-level models in the Prolog language. This high-level modeling makes it possible to describe chip and board functions at an adequate level of accuracy without giving useless details. Each chip is successfully considered as a test goal; difficult chips are identified. Design modifications in terms of multiplexers or scan path insertion are proposed according to a test strategy. As a final result of this analysis, the test planning (test data flow and test control, test scheduling) is defined. The resulting test program skeleton is then formatted to lead to the final test program.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117022274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
The role of test in a 'continuous improvement' environment 测试在“持续改进”环境中的作用
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82312
R. Santella
{"title":"The role of test in a 'continuous improvement' environment","authors":"R. Santella","doi":"10.1109/TEST.1989.82312","DOIUrl":"https://doi.org/10.1109/TEST.1989.82312","url":null,"abstract":"Manufacturing companies are employing strategies such as JIT/TQC (just in time/total quality control) to achieve continuous improvement'. It is suggested that the key to quality in a continuous improvement environment is the reduction of critical parameter process variation through an ongoing pursuit of process-related continuous improvement. It is further argued that the only way companies will be able to tell whether process improvement is in fact taking place is by having statistically capable, precise, accurate, stable, and controlled measurement and test processes. The role of the test professionals working in the continuous improvement arena will be to develop these processes. Their job will be to add value to the processes which produce the customers' products.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"172 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120871156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design assurance in a university setting 大学环境下的设计保证
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82303
K. Rose
{"title":"Design assurance in a university setting","authors":"K. Rose","doi":"10.1109/TEST.1989.82303","DOIUrl":"https://doi.org/10.1109/TEST.1989.82303","url":null,"abstract":"It is argued that VLSI design assurance in a university setting requires developing an environment in which a multiplicity of reliable designs can be produced by inexperienced designers at minimal costs. Two issues in design verification and testing are examined: the first relates to design for testability; the second is the practical verification of designs once they are implemented in silicon. It is concluded that as problems associated with design assurance are solved, the results should be of value to a broader community and especially to ASIC (application-specific integrated circuit) designers.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124498342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An optimal test sequence for the JTAG/IEEE P1149.1 test access port controller JTAG/IEEE P1149.1测试接入端口控制器的最佳测试顺序
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82277
A. Dahbura, M. U. Uyar, C. W. Yau
{"title":"An optimal test sequence for the JTAG/IEEE P1149.1 test access port controller","authors":"A. Dahbura, M. U. Uyar, C. W. Yau","doi":"10.1109/TEST.1989.82277","DOIUrl":"https://doi.org/10.1109/TEST.1989.82277","url":null,"abstract":"A test sequence is given for the test access port (TAP) controller portion of the boundary-scan architecture proposed by the Joint Test Action Group (JTAG) and IEEE Working Group P1149.1 as an industry-standard design-for-testability technique. The resulting test sequence, generated by using a technique based on Rural Chinese Postman tours and unique input/output sequences, is of minimum cost (time) and rigorously tests the specified functional behavior of the controller. The test sequence can be used for detecting design faults for conformance testing or for detecting manufacture-time/run-time defects/faults.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129854367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 46
CrossCheck-a practical solution for ASIC testability 交叉检查- ASIC可测试性的实用解决方案
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82381
G. Swan, Y. Trivedi, D. J. Wharton
{"title":"CrossCheck-a practical solution for ASIC testability","authors":"G. Swan, Y. Trivedi, D. J. Wharton","doi":"10.1109/TEST.1989.82381","DOIUrl":"https://doi.org/10.1109/TEST.1989.82381","url":null,"abstract":"It is noted that testing ASICs (application-specific integrated circuits) has become a significant problem for engineers; manual generation of test patterns is too time consuming, and automatic generation of test patterns is very difficult, if not impossible, without imposing significant overheads on the design. It is shown that this challenge can be addressed by an innovative solution called CrossCheck. The CrossCheck method fundamentally solves the problem by using a combination of software and hardware techniques. The hardware portion of the technology involves modifying the base array of an ASIC such that it contains a structure similar to a bed of nails. This embedded probe structure provides massive observability within the design, which in turn makes it inherently testable. The software can then take advantage of this testability by providing a set of high-performance tools (typically 40 times faster) which will fault simulate/test generate a broad range of manufacturing defects, including transistor opens and shorts or net opens and shorts. The authors give an overview of the technology and then describe probable defects which may occur in CMOS. They conclude that adoption of CrossCheck allows unprecedented levels of fault coverage and chip or board diagnosis to be achieved.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130932737","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A framework and method for hierarchical test generation 分层测试生成的框架和方法
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82331
J. Calhoun, F. Brglez
{"title":"A framework and method for hierarchical test generation","authors":"J. Calhoun, F. Brglez","doi":"10.1109/TEST.1989.82331","DOIUrl":"https://doi.org/10.1109/TEST.1989.82331","url":null,"abstract":"The authors have proposed and implemented a dynamic framework and a method for hierarchically generating test patterns from a hierarchical net list. They have shown consistent gains in CPU over the traditional gate-level implementation while maintaining identical levels of fault coverage. In generating and characterizing modules for a large and varied set of hierarchical benchmarks, the authors benefited considerably from the consistent representations that are available during synthesis from a high-level description or when modules are generated by a process of technology mapping into standard cells. The authors introduced the concept of a single generic module which is hierarchical; the traditional AND, OR, NAND, and NOR are included implicitly. They developed a module-oriented decision-making algorithm, MODEM, which entails a dynamic calculus and procedures such as implication, error propagation, line justification, and probabilistic testability measures for a single generic module. Without loss of generality they adapted the control flow and basic features of PODEM in the first implementation of MODEM.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126837877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 63
Practical test strategies for users of 100 p.p.m. ICs 100ppm集成电路用户的实用测试策略
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82311
J. Westover
{"title":"Practical test strategies for users of 100 p.p.m. ICs","authors":"J. Westover","doi":"10.1109/TEST.1989.82311","DOIUrl":"https://doi.org/10.1109/TEST.1989.82311","url":null,"abstract":"It is noted that in 1980s, integrated circuit suppliers have made major improvements in their product quality. As a result, users are receiving large volumes of devices with failure rates of less than 100 p.p.m.. This has provided users with alternatives to 100% testing, such as dock-to-stock and just-in-time programs. Although the quality of devices has improved, lots with reject rates exceeding 10000 p.p.m. continue to be reported. The author presents test results that demonstrate that quality variations from suppliers continue to occur. It is concluded that users should consider current results and carefully develop, from the many strategies available, their own strategies for reducing test costs while minimizing the risk of accepting defective devices. A number of test strategies and their applications are outlined.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114065971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Reconfigurable resource architecture improves VLSI tester utilization 可重构资源架构提高了VLSI测试仪的利用率
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82346
S. O'Keefe
{"title":"Reconfigurable resource architecture improves VLSI tester utilization","authors":"S. O'Keefe","doi":"10.1109/TEST.1989.82346","DOIUrl":"https://doi.org/10.1109/TEST.1989.82346","url":null,"abstract":"A VLSI tester which can be reconfigured from one high pin count test head to multiple independent lower pin count test heads is described. This reconfigurable resource architecture is shown to provide improved tester utilization for the factory. Greater utilization results in reduced capital equipment costs, thus reducing test costs for the test equipment user. A reconfigurable resource architecture also provides greater flexibility for future upgrades as a result of changing pin count combinations or increased pin count.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114182164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信