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Proceedings. 'Meeting the Tests of Time'., International Test Conference最新文献

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STEED-a testability enhancement expert design system steed -可测试性增强专家设计系统
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82398
D. Koehler, A. Somani
{"title":"STEED-a testability enhancement expert design system","authors":"D. Koehler, A. Somani","doi":"10.1109/TEST.1989.82398","DOIUrl":"https://doi.org/10.1109/TEST.1989.82398","url":null,"abstract":"A description is given of STEED (testability enhancement expert design system) which has been built to perform testability analysis and design rule checking on circuit board designs at an avionics firm. STEED is able to identify correctly several common circuit features which make a circuit untestable (or are bad design practice). STEED provides a measure of 'expert' advice at a low time and effort overhead to the design engineer. It automates the testability design process and helps to ensure that a circuit meets the testability design rules.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"199 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121397043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A self-test system architecture for reconfigurable WSI 一种用于可重构WSI的自检系统体系结构
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82308
D. Landis
{"title":"A self-test system architecture for reconfigurable WSI","authors":"D. Landis","doi":"10.1109/TEST.1989.82308","DOIUrl":"https://doi.org/10.1109/TEST.1989.82308","url":null,"abstract":"Progress in wafer scale integration (WSI) has brought the problem of electronic system testing into the semiconductor manufacturing arena. The problem is complicated by the reduced controllability and observability implicit at the full wafer integration level. Structured methods must be employed to generate and apply tests in a hierarchical fashion at the function, chip, and system levels. The author describes a methodology which addresses these problems for both the manufacturing and field test environments. A uniform testing interface is defined for each functional chip (cell), with built-in self-test incorporated whenever possible on all new designs. Use of a standard interface will reduce test complexity and costs by allowing entire wafer probing by a common standardized probe card, irrespective of the number of different species of functional cells. Details are provided for the function (cell-), chip-, and wafer-level testing standards, as well as for the procedures to be followed at wafer level restructuring and testing. The proposed methods will allow current generation wafer restructuring methods to be applied to the next generation of WSI designs, which will require numerous cell types and increasing on-wafer complexity.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131118330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A telecommunications line interface test system architecture 一个电信线路接口测试系统架构
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82297
J. LaMay, D. Caldwell
{"title":"A telecommunications line interface test system architecture","authors":"J. LaMay, D. Caldwell","doi":"10.1109/TEST.1989.82297","DOIUrl":"https://doi.org/10.1109/TEST.1989.82297","url":null,"abstract":"The authors present new test techniques which have been used to develop a high-quality, cost-efficient test module suitable for high-volume testing of T1/PCM-39 line interface devices. This test module is capable of fully testing the key parameters of sophisticated line interface driver/receivers (jitter tolerance, jitter attenuation, and pulse-shape template conformance). Using this module, a 75% reduction in test time was achieved. The test system is being used for production testing of ISDN (integrated services digital network) primary-rate line interface devices.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127015592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Fault simulation in a pipelined multiprocessor system 流水线多处理机系统的故障仿真
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82361
P. Agrawal, V. Agrawal, K. Cheng, Raffi Tutundjian
{"title":"Fault simulation in a pipelined multiprocessor system","authors":"P. Agrawal, V. Agrawal, K. Cheng, Raffi Tutundjian","doi":"10.1109/TEST.1989.82361","DOIUrl":"https://doi.org/10.1109/TEST.1989.82361","url":null,"abstract":"The authors describe fault simulation algorithms for the MARS hardware accelerator. Two algorithms are considered. The first, serial fault simulation, has a performance that is linear in the number of faults. Its performance is easily predictable and it takes full advantage of the true-value simulation speed of the accelerator; it is also easy to implement. The second algorithm, concurrent fault simulation, is found to have a performance that is nonlinear in the number of faults. It also requires either a large amount of memory or a dynamic memory management, both of which are difficult to implement in an accelerator. Yet the concurrent method has the advantage of more efficient event processing and less duplicated effort. Combining the features of both algorithms, a fixed-memory, multipass, concurrent algorithm is developed for MARS.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132645269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 41
Location and identification for single and multiple faults in testable redundant PLAs for yield enhancement 可测试冗余pla中单个和多个故障的定位和识别，以提高成品率
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82354
Yinan N. Shen, F. Lombardi
{"title":"Location and identification for single and multiple faults in testable redundant PLAs for yield enhancement","authors":"Yinan N. Shen, F. Lombardi","doi":"10.1109/TEST.1989.82354","DOIUrl":"https://doi.org/10.1109/TEST.1989.82354","url":null,"abstract":"The authors present the basic structure of a testable and repairable programmable logic array (PLA) and the design modifications which are required for a full diagnosis and yield enhancement. The testing process is fully analyzed, and the conditions for diagnosis are presented. It is proved that identification in the presence of multiple (crosspoint, stuck-at, and bridging) faults is possible with high coverage. The criteria which permit diagnosis are based on a hierarchical organization of the testing process; significant improvements over previous redundant structures can be achieved. This results in a compact structure with a homogeneous layout which has been evaluated with respect to area overhead for VLSI implementation. Simulation results for benchmark devices are presented. These suggest that an efficient repair of VLSI PLAs for yield enhancement can be achieved.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134516332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Transmission line simulation for testing ISDN devices 用于测试ISDN设备的传输线模拟
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82281
David K. Oka
{"title":"Transmission line simulation for testing ISDN devices","authors":"David K. Oka","doi":"10.1109/TEST.1989.82281","DOIUrl":"https://doi.org/10.1109/TEST.1989.82281","url":null,"abstract":"A transmission line model has been developed to simulate the effects of sourcing ISDN (integrated services digital network) waveforms through twisted-pair telephone cable. Circuit simulation models for three different wire gauges have been used to predict the transmission characteristics of arbitrary networks using SPICE simulations. These models have been configured to simulate a standard test network specified by ANSI and have demonstrated good correlation with an actual twisted-pair telephone test network. The models correctly simulate the input and output impedances imposed by cable and effectively model the transmission effects of mismatched terminations. From the simulated frequency response, FIR (finite impulse response) filter coefficients can be derived to allow DSP (digital signal processing) of test waveforms. This allows the testing of ISDN transceivers using signals likely to be encountered in their intended application.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"251 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133243212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
CMOS IC stuck-open-fault electrical effects and design considerations CMOS IC卡开故障的电效应及设计考虑
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82325
J. Soden, R. Treece, Michael R. Taylor, C. Hawkins
{"title":"CMOS IC stuck-open-fault electrical effects and design considerations","authors":"J. Soden, R. Treece, Michael R. Taylor, C. Hawkins","doi":"10.1109/TEST.1989.82325","DOIUrl":"https://doi.org/10.1109/TEST.1989.82325","url":null,"abstract":"The authors evaluate CMOS IC stuck-open-fault electrical effects, including voltage levels, quiescent power supply current (I/sub DDQ/), transient response, and important testing considerations. The transient responses of the defective node voltage and power supply current to the high-impedance state caused by a stuck-open defect were measured to determine if the I/sub DDQ/ measurement technique could detect stuck-open faults. The measured transient response of stuck-open faults shows that this defect acts as a memory fault for normal system and tester clock periods. The data also show that detectable elevated I/sub DDQ/ can occur rapidly for some circuit designs. Elevated I/sub DDQ/ can also occur over many clock cycles as the high-impedance node associated with the stuck-open fault undergoes a drift in its voltage. The I/sub DDQ/ technique is interpreted as significantly enhancing the detection of stuck-open defects, but not guaranteeing their detection. Modifications to the circuit layout to reduce the probability of stuck-open-fault occurrence are presented.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133651459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 107
A testability strategy for silicon compilers 硅编译器的可测试性策略
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82353
F. Beenker, R. Dekker, Rudi Stans, Max van der Star
{"title":"A testability strategy for silicon compilers","authors":"F. Beenker, R. Dekker, Rudi Stans, Max van der Star","doi":"10.1109/TEST.1989.82353","DOIUrl":"https://doi.org/10.1109/TEST.1989.82353","url":null,"abstract":"The authors present a testability strategy for complex VLSI devices which is implemented in the PIRAMID Digital Signal Processor Silicon Compiler. The macrotest methodology supports built-in self-test, scan test, bus test control, restricted partial scan and test control logic at various levels in the design hierarchy. A set of testability design rules is developed and implemented automatically in the design. The design hierarchy is closely followed, resulting in a hierarchical set of testable macros. The complete process from design to final test program is guided by software tools. As an example, the synthesis of a large industrial circuit is presented for comparing the proposed approach with the traditional approaches. The additional overhead due to testability is within reasonable limits (roughly 8%), and the software run time figures show that it is possible to generate a test program with an excellent fault coverage within a very short period of time.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"508 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116331109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Techniques for improved testability in the IBM ES/9370 system 改进IBM ES/9370系统可测试性的技术
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82310
R. Lusch, Endre F. Sarkany
{"title":"Techniques for improved testability in the IBM ES/9370 system","authors":"R. Lusch, Endre F. Sarkany","doi":"10.1109/TEST.1989.82310","DOIUrl":"https://doi.org/10.1109/TEST.1989.82310","url":null,"abstract":"The authors discuss three techniques used in the IBM ES/9370 series of processors to improve the testability, and hence the quality levels, of card assemblies. First they investigate the testing requirements and challenges presented by a nonvolatile static RAM and how they were met. Then they introduce a method which uses flush-through logic to provide improved access to array components. Next, the authors discuss how a compare circuit can be used to reduce I/O (input/output) requirements when testing an array. These algorithms were successfully implemented using programming Language for Testing (PLT). Background information and a detailed methodology for each of the techniques are provided.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117004783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An integrated analog test simulation environment 集成模拟测试仿真环境
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82341
Bruce A. Webster
{"title":"An integrated analog test simulation environment","authors":"Bruce A. Webster","doi":"10.1109/TEST.1989.82341","DOIUrl":"https://doi.org/10.1109/TEST.1989.82341","url":null,"abstract":"An integrated test simulation environment which links circuit simulation data and tester simulation is presented. This environment is critical to the computer-aided development of test packages for analog integrated circuits. A working example is presented. The overall benefit of the integrated simulation environment described is a shortening of the test development cycle. By allowing the test engineer to begin test package development earlier, the overall, IC design/test process shifts from a serial task to one with significant overlap.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"287 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123433430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
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