{"title":"steed -可测试性增强专家设计系统","authors":"D. Koehler, A. Somani","doi":"10.1109/TEST.1989.82398","DOIUrl":null,"url":null,"abstract":"A description is given of STEED (testability enhancement expert design system) which has been built to perform testability analysis and design rule checking on circuit board designs at an avionics firm. STEED is able to identify correctly several common circuit features which make a circuit untestable (or are bad design practice). STEED provides a measure of 'expert' advice at a low time and effort overhead to the design engineer. It automates the testability design process and helps to ensure that a circuit meets the testability design rules.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"199 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"STEED-a testability enhancement expert design system\",\"authors\":\"D. Koehler, A. Somani\",\"doi\":\"10.1109/TEST.1989.82398\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A description is given of STEED (testability enhancement expert design system) which has been built to perform testability analysis and design rule checking on circuit board designs at an avionics firm. STEED is able to identify correctly several common circuit features which make a circuit untestable (or are bad design practice). STEED provides a measure of 'expert' advice at a low time and effort overhead to the design engineer. It automates the testability design process and helps to ensure that a circuit meets the testability design rules.<<ETX>>\",\"PeriodicalId\":264111,\"journal\":{\"name\":\"Proceedings. 'Meeting the Tests of Time'., International Test Conference\",\"volume\":\"199 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1989-08-29\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings. 'Meeting the Tests of Time'., International Test Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/TEST.1989.82398\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TEST.1989.82398","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
STEED-a testability enhancement expert design system
A description is given of STEED (testability enhancement expert design system) which has been built to perform testability analysis and design rule checking on circuit board designs at an avionics firm. STEED is able to identify correctly several common circuit features which make a circuit untestable (or are bad design practice). STEED provides a measure of 'expert' advice at a low time and effort overhead to the design engineer. It automates the testability design process and helps to ensure that a circuit meets the testability design rules.<>
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