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Proceedings. 'Meeting the Tests of Time'., International Test Conference最新文献

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Process monitoring oriented IC testing 过程监控导向的IC测试
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82336
Wojciech Maly, Samir B. Naik
{"title":"Process monitoring oriented IC testing","authors":"Wojciech Maly, Samir B. Naik","doi":"10.1109/TEST.1989.82336","DOIUrl":"https://doi.org/10.1109/TEST.1989.82336","url":null,"abstract":"The authors proposed the use of functional testing for the extraction of IC manufacturing defect characteristics. It is demonstrated, using an SRAM (static random-access memory) example, that such extraction is feasible if an appropriate methodology for the interpretation of testing results is applied. The methodology allows for the extraction of information about process disturbances and abnormalities causing IC malfunctions. In this methodology the Monte Carlo fault modeling technique, combined with circuit simulation, was applied to build a defect fault vocabulary. The simulation experiment conducted by using this methodology demonstrated that a spectrum of signatures can be created to represent process disturbances. It was also shown that such a spectrum of signatures can be sensitive enough to changes in the defect densities.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125188658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Hardware-based weighted random pattern generation for boundary scan 基于硬件的边界扫描加权随机模式生成
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82307
F. Brglez, G. Kedem, C. Gloster
{"title":"Hardware-based weighted random pattern generation for boundary scan","authors":"F. Brglez, G. Kedem, C. Gloster","doi":"10.1109/TEST.1989.82307","DOIUrl":"https://doi.org/10.1109/TEST.1989.82307","url":null,"abstract":"The authors introduce WARP, a weighted test generation system that includes a canonical circuit for resolving weights to any desired precision. Either cellular automata registers (CARs) or linear feedback shift registers (LFSRs) are used as a source of random patterns, and optionally, it is possible to permute and linearly combine random bits from the source to control inputs to the weighting circuit. The authors analyze pattern coverage and conclude with benchmark results on fault coverage differences between CARs and LFSRs.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124350827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 102
Fault diagnosis in analogue circuits using AI techniques 基于人工智能技术的模拟电路故障诊断
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82285
A. McKeon, A. Wakeling
{"title":"Fault diagnosis in analogue circuits using AI techniques","authors":"A. McKeon, A. Wakeling","doi":"10.1109/TEST.1989.82285","DOIUrl":"https://doi.org/10.1109/TEST.1989.82285","url":null,"abstract":"The authors describe a technique for detecting and locating faults in analogue circuits by checking that the measurements are consistent with the circuit function. The unique representation used accommodates the imprecise nature of analogue circuits. A model of the circuit is formed from the constraints imposed by the behavior of the components and the interconnections. The values of parameters within the circuit are deduced by propagating the effects of measurements through this model. Faults are implied from the detection of inconsistencies and located by suspending constraints within the model. The method does not use fault simulation and is therefore applicable to any type of fault. It is able to detect performance variations, as well as catastrophic failures. Values are represented as ranges within which the true value lies. This overcomes the difficulty of representing the uncertainty inherent in any analogue design or measurements. The method has been successfully used to detect and locate a number of faults in several circuits.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122357688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 38
Parallel automated test pattern generation on the Connection Machine 在连接机上并行自动测试模式生成
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82394
Pankaj Mayor, Vijay Pitchumani, Vinod Narayanan
{"title":"Parallel automated test pattern generation on the Connection Machine","authors":"Pankaj Mayor, Vijay Pitchumani, Vinod Narayanan","doi":"10.1109/TEST.1989.82394","DOIUrl":"https://doi.org/10.1109/TEST.1989.82394","url":null,"abstract":"The authors present an SIMD (single-instruction multiple-data) algorithm for automated test pattern generation. An effort was made to parallelize the individual steps of FAN by employing the massive parallelism of the Connection Machine. The algorithm considers one fault at a time and generates a test for it. Fine-grain parallelism is achieved by several gates within a level simultaneously doing multiple backtrace or forward simulation.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129924452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
R96MFX test strategy R96MFX测试策略
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82348
W. Mann
{"title":"R96MFX test strategy","authors":"W. Mann","doi":"10.1109/TEST.1989.82348","DOIUrl":"https://doi.org/10.1109/TEST.1989.82348","url":null,"abstract":"The author describes the design for test features and overall test strategy for the R96MFX integrated circuit. This product is a 9600-b-per second half duplex modem used in facsimile equipment. It is implemented by two separate silicon dies mounted within one 64-pin package. Each of these two circuits had been previously designed and used in separate packages, so combining them in one package resulted in an I/O (input/output) pin consolidation which seriously limited the circuits' controllability and observability. The test strategy utilized to solve this limitation relies on the complementary test that IC manufacturers may perform; that is, they may thoroughly test a device at the wafer level and then test the device again after packaging for those failures induced by the packaging process. A self-test feature was implemented in the firmware instructions in one of the two chips thereby enabling extensive testing to be accomplished in spite of the controllability/observability limitations.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125152554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Built in self test of the Macrolan chip 内置自我测试的Macrolan芯片
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82362
R. Illman, S. Clarke
{"title":"Built in self test of the Macrolan chip","authors":"R. Illman, S. Clarke","doi":"10.1109/TEST.1989.82362","DOIUrl":"https://doi.org/10.1109/TEST.1989.82362","url":null,"abstract":"The authors describe the experience of implementing self-test in the medium access controller (MAC) chip for the Macrolan advanced fiber-optic local area network system. The CMOS chip contains approximately 35K gates and 200 logic pins, and has been designed using a semi-custom-design approach based on a parameterized cell library. The implementation of BIST (built-in self-test) for this chip has highlighted problems with some conventional BIST techniques and led to the adoption of new test styles. In particular, quasi-exhaustive test has been widely used for testing combinatorial logic within the chip. Also the tradeoffs involved in testing embedded memories and the assumptions on modeling random pattern testing of such memories have been closely investigated. It is concluded that the methodology described allows ASICs (application-specific integrated circuits) to be designed with full BIST.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126883185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Qualification and quantification of process-induced product-related defects 对过程引起的产品相关缺陷进行鉴定和量化
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82351
F. Camerik, P. J. Dirks, J. Jess
{"title":"Qualification and quantification of process-induced product-related defects","authors":"F. Camerik, P. J. Dirks, J. Jess","doi":"10.1109/TEST.1989.82351","DOIUrl":"https://doi.org/10.1109/TEST.1989.82351","url":null,"abstract":"The authors report research concerning the effects of inaccurate silicon processing on integrated circuits. To acquire information about defective processing steps, electrical measurements applied to defect monitors or product yield modules (PYMs) are proposed. The authors describe two such PYMs derived from a 128K SRAM matrix, as well as the kinds of measurements that should be carried out and the way they should be evaluated to obtain defect density data for yield prediction. In addition, the authors present some new theoretical results concerning the actual ability of defect monitors to deliver reliable results. They also consider the complexity of the measuring procedure. It turns out that, depending on the flexibility of the experimental setup, this complexity is more significantly dependent on the number of defects to be detected than on the complexity of the monitor structure.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"102 19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127253944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A new framework for analyzing test generation and diagnosis algorithms for wiring interconnects 一种新的分析布线互连测试生成和诊断算法的框架
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82278
N. Jarwala, C. W. Yau
{"title":"A new framework for analyzing test generation and diagnosis algorithms for wiring interconnects","authors":"N. Jarwala, C. W. Yau","doi":"10.1109/TEST.1989.82278","DOIUrl":"https://doi.org/10.1109/TEST.1989.82278","url":null,"abstract":"A novel framework for analyzing test generation and diagnosis algorithms for wiring interconnect are presented. A property of test vector sets, called diagonal independence, which guarantees the diagnostic resolution of the vector test set is identified. The failing responses or syndromes are classified into aliasing and confounding syndromes, and this classification permits precise analysis of the diagnostic capabilities of different test algorithms. Using this framework, all the algorithms that have been proposed for board interconnect testing are analyzed. Their capabilities and limitations are clearly defined. A new optimal adaptive algorithm that can reduce test and diagnosis complexity is also presented.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126669167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 165
Signature analysis with non-linear feedback shift registers 非线性反馈移位寄存器的特征分析
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82405
P. Marinos, R. Raina
{"title":"Signature analysis with non-linear feedback shift registers","authors":"P. Marinos, R. Raina","doi":"10.1109/TEST.1989.82405","DOIUrl":"https://doi.org/10.1109/TEST.1989.82405","url":null,"abstract":"The use of nonlinear feedback shift registers (NLFSRs) in the design of signature analyzers (SAs) was investigated. It is shown that SAs with arbitrarily low values of error-escape probability and requiring less hardware than their linear feedback shift register (LFSR) counterparts are feasible and systematically realizable.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"37 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133005848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A testable realization of CMOS combinational circuits CMOS组合电路的可测试实现
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82334
S. Chakravarty
{"title":"A testable realization of CMOS combinational circuits","authors":"S. Chakravarty","doi":"10.1109/TEST.1989.82334","DOIUrl":"https://doi.org/10.1109/TEST.1989.82334","url":null,"abstract":"The KR realization (see S. Kundu and S.M. Reddy, Proc. 18th Int. Fault-Tolerant Computing Symp., p.220-25 1988) was proposed with the aim of designing testable CMOS combinational circuits using only primitive gates and no extraneous hardware. It is shown that for some useful Boolean functions the size of the KR realization is exponential in the number of input variables. The author presents a testable realization of a CMOS combinational circuit, with respect to FET (field-effect-transistor) stuck-open faults, named FM-CMOS. It uses only two-input multiplexers and, to an extent, addresses the size-problem of the KR realization. More specifically, it is shown that for some useful Boolean functions for which the size of the KR realization is exponential in the number of input variables the size of the FM-CMOS realization is polynomial in the number of input variables. For this reason, it is proposed that the FM-CMOS realization be used in conjunction with the KR realization. The results are applied to design a testable n-b CMOS adder that uses only O(n) FETs.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114061229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
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