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Proceedings. 'Meeting the Tests of Time'., International Test Conference最新文献

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Flexible, high-performance pin electronics implementation 灵活，高性能的引脚电子实现
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82367
P. King
{"title":"Flexible, high-performance pin electronics implementation","authors":"P. King","doi":"10.1109/TEST.1989.82367","DOIUrl":"https://doi.org/10.1109/TEST.1989.82367","url":null,"abstract":"The author discusses an implementation of the pin electronics for a distributed architecture (resource-per-pin) printed circuit board test system. Included are descriptions of the custom integrated circuits and hybrids used to accomplish this at a reasonable cost. The pin electronics card which incorporates these custom parts is a relatively sparse looking 16-in by 20.5-in assembly. It is densely routed on six layers using conservative design rules (25-mil line pitch) to achieve the required interconnect. These custom parts allow the automatic compensation for many of the error terms found in a high-performance board test system. The present work demonstrates that it is possible to add significantly to the functionality of printed circuit board test systems through the use of custom integrated circuits. This added functionality can be used to provide new test capabilities and to make existing capabilities easier to use, thereby helping the user meet demanding test requirements. Along with the functionality improvements come equally important accuracy, reliability, and cost benefits.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134129629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Combinational and sequential circuit fault diagnosis using AI techniques 利用人工智能技术进行组合和顺序电路故障诊断
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82401
B. Rogel-Favila, P. Cheung
{"title":"Combinational and sequential circuit fault diagnosis using AI techniques","authors":"B. Rogel-Favila, P. Cheung","doi":"10.1109/TEST.1989.82401","DOIUrl":"https://doi.org/10.1109/TEST.1989.82401","url":null,"abstract":"The authors describe an algorithm for the location of faults in digital circuits. It is based on the 'deep reasoning' approach to circuit fault diagnosis, and since a failure is defined as a mismatch between expected and measured behavior, it can deal with a wider range of different types of faults than traditional approaches. The application of the diagnosis procedure to examples of combinational and sequential circuits gives encouraging results.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125906185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Model engineering curricula for 'meeting the tests of time' “迎接时间考验”的工程课程示范
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82400
R. Absher, J. Lecky
{"title":"Model engineering curricula for 'meeting the tests of time'","authors":"R. Absher, J. Lecky","doi":"10.1109/TEST.1989.82400","DOIUrl":"https://doi.org/10.1109/TEST.1989.82400","url":null,"abstract":"A curriculum in electronics test engineering is outlined. Typical program requirements are presented.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126331436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
IC characteristic matching for optimal system performance 集成电路特性匹配，优化系统性能
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82313
Kenneth R. Stuchlik
{"title":"IC characteristic matching for optimal system performance","authors":"Kenneth R. Stuchlik","doi":"10.1109/TEST.1989.82313","DOIUrl":"https://doi.org/10.1109/TEST.1989.82313","url":null,"abstract":"The author addresses integrated-circuit performance characteristic-matching considerations for which multiple suppliers or technologies are required. It is suggested that, in order to ensure robust designs in high-performance systems, the variability between the required devices and suppliers should be minimized. The variability can be minimized through the evaluation of the critical performance characteristics, both specified and nonspecified, of all desired suppliers and technologies. The selection of suppliers or technologies may then be limited to those which are the most compatible or to a source with the most desirable characteristics. As performance requirements increase, the current specification methods and the parameters specified are becoming less and less adequate to ensure consistency in the design and manufacture of modern high-performance systems. A more desirable method may be to specify target means and distributions versus minimum/maximum limits. In addition, the requirement to specify performance-related parameters. Such as speed performance offsets or dynamic high- and/or low-level input voltage levels, should also be pursued. As an example, an outline of a basic study of the 74FXXX family of devices is presented.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127095637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Testing and testability of programmable logic devices 可编程逻辑器件的测试和可测试性
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82396
J. VanDerwiele
{"title":"Testing and testability of programmable logic devices","authors":"J. VanDerwiele","doi":"10.1109/TEST.1989.82396","DOIUrl":"https://doi.org/10.1109/TEST.1989.82396","url":null,"abstract":"The author emphasizes that it is critical that thorough testing of programmable logic devices be included in the manufacturing process. Part of this testing is often done in the in-circuit test environment. It is concluded that testability must be programmed into these parts for successful in-circuit testing.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125183889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Achieving ATE accuracy at gigahertz test rates: comparison of electronic and electrooptic sampling technologies 在千兆赫测试速率下实现ATE精度:电子和电光采样技术的比较
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82404
F.J. Henley, H. Choi
{"title":"Achieving ATE accuracy at gigahertz test rates: comparison of electronic and electrooptic sampling technologies","authors":"F.J. Henley, H. Choi","doi":"10.1109/TEST.1989.82404","DOIUrl":"https://doi.org/10.1109/TEST.1989.82404","url":null,"abstract":"Testing devices at clock rates exceeding 50 MHz with waveform resolution below 100 ps necessitates the use of sampling methods. The current state of the art includes two radically different sampling technologies: electronic sampling (ES) utilizing a diode bridge structure and a novel electrooptic sampling (EOS) technology which uses short light pulses as the time-resolving element. The bandwidth, loading, and time/voltage accuracy of these two technologies are compared for fitness of use in a gigahertz ATE (automatic test equipment) environment. It is noted that the analysis of these two techniques quantifies the electrooptic technology's time accuracy advantages due to its low loading and short DUT (device under test)/sensor distances.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122892546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Quality issues of high pin count fine pitch VLSI packages 高引脚数小间距VLSI封装的质量问题
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82324
E. Hnatek, B. R. Livesay
{"title":"Quality issues of high pin count fine pitch VLSI packages","authors":"E. Hnatek, B. R. Livesay","doi":"10.1109/TEST.1989.82324","DOIUrl":"https://doi.org/10.1109/TEST.1989.82324","url":null,"abstract":"The continuous demand for both high-speed integrated circuits of all types and increased on-chip circuitry density is fueling the need for high-pin-count (>256), fine-line (<or=20 mil) packages. In the past the package served primarily as mechanical protection for the chip and as a convenient way to bring signals from the chip to the next level of packaging. With the rapid growth in the use of VLSI circuits, increasing thought must be given to the design of the package. The authors show that the quality of high-pin-count, fine-pitch VLSI packages is complex and dependent on a multiplicity of issues: electrical, testing and tester, thermal management, and materials/interface. They conclude that each of these must be addressed to yield a quality package. Further, the limiting factors to the widespread use of VLSI circuits will be the ability to test these devices accurately and effectively, as well as the ability to package the die reliably and provide an efficient connection to the external world.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129945979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Rapid data acquisition for e-beam testing 电子束测试的快速数据采集
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82385
D. Hall, A. Sloman, G. Plows
{"title":"Rapid data acquisition for e-beam testing","authors":"D. Hall, A. Sloman, G. Plows","doi":"10.1109/TEST.1989.82385","DOIUrl":"https://doi.org/10.1109/TEST.1989.82385","url":null,"abstract":"A system (EBT 2000) for increasing the speed of signal acquisition in electron-beam testing is described. The system produces a number of beam unblanking pulses per test cycle in a manner similar to that used by sampling oscilloscopes. A new waveform recovery system has been designed that gives throughput improvements of up to 1000 times. Stroboscopic image acquisition times are also improved by a factor of up to 64. The increased speed of data acquisition generally enhances instrument applications, while the implementation of burst mode imaging will specifically improve techniques such as dynamic fault imaging, which depend upon the bulk acquisition of stroboscopic images.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131030507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A new array architecture for parallel testing in VLSI memories 一种用于VLSI存储器并行测试的新型阵列结构
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82315
Y. Matsuda, K. Arimoto, M. Tsukude, T. Oishi, K. Fujishima
{"title":"A new array architecture for parallel testing in VLSI memories","authors":"Y. Matsuda, K. Arimoto, M. Tsukude, T. Oishi, K. Fujishima","doi":"10.1109/TEST.1989.82315","DOIUrl":"https://doi.org/10.1109/TEST.1989.82315","url":null,"abstract":"The authors describe a novel array architecture and its application to a 16-Mb DRAM (dynamic random-access memory) suitable for the line mode test (LMT) with test circuits consisting of a multipurpose register (MPR) and a comparator. The LMT can test all memory cells connected to a word line simultaneously. Testing with random patterns along a word line is easily realized by using the MPR as a pattern register after setting random test data in the MPR. Test time is reduced to approximately 1/1000. Owing to the MPR, the present LMT can achieve flexible testing with high fault coverage. The excess area penalty due to the circuits for the LMT is suppressed within 0.5% in application to the 16-Mb DRAM.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130709473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
The linear array systolic tester (LAST) 线性阵列收缩测试仪(LAST)
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82338
Gary J. Lesmeister
{"title":"The linear array systolic tester (LAST)","authors":"Gary J. Lesmeister","doi":"10.1109/TEST.1989.82338","DOIUrl":"https://doi.org/10.1109/TEST.1989.82338","url":null,"abstract":"A description is given of the LAST system, a linear string of systolic processors connected together to provide a stimulus/response testing function to a device under test (DUT). LAST addresses a major problem in tester design by reducing the data transfer/storage requirements. LAST accomplishes this by converting the rhythm and regularity found in VLSI and ASIC (application-specific integrated circuit) test vector patterns into independent systolic processor rhythms. This rhythm conversion reduces the data processing and handling by orders of magnitude. LAST integrates an APG (automatic pattern generator) function at each channel, which reduces vector memory requirements for the regular test vector structures encountered in today's ASIC parts.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123056949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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