Flexible, high-performance pin electronics implementation

P. King
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引用次数: 2

Abstract

The author discusses an implementation of the pin electronics for a distributed architecture (resource-per-pin) printed circuit board test system. Included are descriptions of the custom integrated circuits and hybrids used to accomplish this at a reasonable cost. The pin electronics card which incorporates these custom parts is a relatively sparse looking 16-in by 20.5-in assembly. It is densely routed on six layers using conservative design rules (25-mil line pitch) to achieve the required interconnect. These custom parts allow the automatic compensation for many of the error terms found in a high-performance board test system. The present work demonstrates that it is possible to add significantly to the functionality of printed circuit board test systems through the use of custom integrated circuits. This added functionality can be used to provide new test capabilities and to make existing capabilities easier to use, thereby helping the user meet demanding test requirements. Along with the functionality improvements come equally important accuracy, reliability, and cost benefits.<>
灵活,高性能的引脚电子实现
本文讨论了一种分布式结构(资源/引脚)印刷电路板测试系统的引脚电子学实现方法。包括用于以合理的成本实现这一目标的定制集成电路和混合电路的描述。集成了这些定制部件的pin电子卡是一个相对稀疏的16英寸乘20.5英寸的组装体。它使用保守的设计规则(25mil线间距)在六层上密集布线,以实现所需的互连。这些定制部件允许对高性能电路板测试系统中发现的许多错误项进行自动补偿。目前的工作表明,通过使用定制集成电路,可以显著增加印刷电路板测试系统的功能。这个添加的功能可以用来提供新的测试功能,并使现有的功能更容易使用,从而帮助用户满足苛刻的测试需求。随着功能的改进,同样重要的是准确性、可靠性和成本效益。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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