The linear array systolic tester (LAST)

Abstract

A description is given of the LAST system, a linear string of systolic processors connected together to provide a stimulus/response testing function to a device under test (DUT). LAST addresses a major problem in tester design by reducing the data transfer/storage requirements. LAST accomplishes this by converting the rhythm and regularity found in VLSI and ASIC (application-specific integrated circuit) test vector patterns into independent systolic processor rhythms. This rhythm conversion reduces the data processing and handling by orders of magnitude. LAST integrates an APG (automatic pattern generator) function at each channel, which reduces vector memory requirements for the regular test vector structures encountered in today's ASIC parts.<>