{"title":"集成模拟测试仿真环境","authors":"Bruce A. Webster","doi":"10.1109/TEST.1989.82341","DOIUrl":null,"url":null,"abstract":"An integrated test simulation environment which links circuit simulation data and tester simulation is presented. This environment is critical to the computer-aided development of test packages for analog integrated circuits. A working example is presented. The overall benefit of the integrated simulation environment described is a shortening of the test development cycle. By allowing the test engineer to begin test package development earlier, the overall, IC design/test process shifts from a serial task to one with significant overlap.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"287 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"14","resultStr":"{\"title\":\"An integrated analog test simulation environment\",\"authors\":\"Bruce A. Webster\",\"doi\":\"10.1109/TEST.1989.82341\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An integrated test simulation environment which links circuit simulation data and tester simulation is presented. This environment is critical to the computer-aided development of test packages for analog integrated circuits. A working example is presented. The overall benefit of the integrated simulation environment described is a shortening of the test development cycle. By allowing the test engineer to begin test package development earlier, the overall, IC design/test process shifts from a serial task to one with significant overlap.<<ETX>>\",\"PeriodicalId\":264111,\"journal\":{\"name\":\"Proceedings. 'Meeting the Tests of Time'., International Test Conference\",\"volume\":\"287 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1989-08-29\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"14\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings. 'Meeting the Tests of Time'., International Test Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/TEST.1989.82341\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TEST.1989.82341","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An integrated test simulation environment which links circuit simulation data and tester simulation is presented. This environment is critical to the computer-aided development of test packages for analog integrated circuits. A working example is presented. The overall benefit of the integrated simulation environment described is a shortening of the test development cycle. By allowing the test engineer to begin test package development earlier, the overall, IC design/test process shifts from a serial task to one with significant overlap.<>
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