CMOS IC stuck-open-fault electrical effects and design considerations

Abstract

The authors evaluate CMOS IC stuck-open-fault electrical effects, including voltage levels, quiescent power supply current (I/sub DDQ/), transient response, and important testing considerations. The transient responses of the defective node voltage and power supply current to the high-impedance state caused by a stuck-open defect were measured to determine if the I/sub DDQ/ measurement technique could detect stuck-open faults. The measured transient response of stuck-open faults shows that this defect acts as a memory fault for normal system and tester clock periods. The data also show that detectable elevated I/sub DDQ/ can occur rapidly for some circuit designs. Elevated I/sub DDQ/ can also occur over many clock cycles as the high-impedance node associated with the stuck-open fault undergoes a drift in its voltage. The I/sub DDQ/ technique is interpreted as significantly enhancing the detection of stuck-open defects, but not guaranteeing their detection. Modifications to the circuit layout to reduce the probability of stuck-open-fault occurrence are presented.<>