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Proceedings. 'Meeting the Tests of Time'., International Test Conference最新文献

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Optimized synthesis of dedicated controllers with concurrent checking capabilities 具有并发检查能力的专用控制器的优化综合
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82319
R. Leveugle, G. Saucier
{"title":"Optimized synthesis of dedicated controllers with concurrent checking capabilities","authors":"R. Leveugle, G. Saucier","doi":"10.1109/TEST.1989.82319","DOIUrl":"https://doi.org/10.1109/TEST.1989.82319","url":null,"abstract":"The authors present a novel synthesis method of dedicated controllers which aims at the detection of faults which cause errors in the state sequences. The state code flow is compacted through polynomial division. An implicit 'justifying signature' method is applied at the state code level and ensures identical signatures before each join node of the control flow graph. The signatures are then independent of the path followed previously in the graph, and the comparison with reference data is greatly facilitated. This property is obtained by a clever state assignment, nearly without area overhead. The controllers can therefore be checked by signature analysis, either by a built-in monitor or by an external checker. The software implementation of the synthesis tool is presented, and the hardware implementation of the concurrent checking is described.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121264515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Fault location in repairable programmable logic arrays 可编程序逻辑阵列的故障定位
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82355
Caribbean Way
{"title":"Fault location in repairable programmable logic arrays","authors":"Caribbean Way","doi":"10.1109/TEST.1989.82355","DOIUrl":"https://doi.org/10.1109/TEST.1989.82355","url":null,"abstract":"In order to ensure the manufacture of large PLA (programmable logic array) chips with reasonable yield level, a design for repairable PLAs (RPLAs) was proposed in which the partially defective chips can be repaired without reconfiguring the external routing. However, before a defective chip can be repaired, the locations of the defects must be precisely identified. The author presents a fault location (diagnosis) scheme that achieves a full diagnosability in locating all single and multiple stuck-at, bridging, and crosspoint faults. Two examples are given to demonstrate the proposed scheme.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121298790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
The analysis of parallel BIST by the combined Markov chain (CMC) model 用联合马尔可夫链(CMC)模型分析并行BIST
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82317
C. Chuang, Anup K. Gupta
{"title":"The analysis of parallel BIST by the combined Markov chain (CMC) model","authors":"C. Chuang, Anup K. Gupta","doi":"10.1109/TEST.1989.82317","DOIUrl":"https://doi.org/10.1109/TEST.1989.82317","url":null,"abstract":"It is shown that the simple Markov chain model used to define the parallel BIST (built-in self-test) technique (see K. Kim et al., IEEE Trans. CAD Integrated Circuits Syst., p.919-28, Aug. 1988) does not work well for state machines. Instead, a combined Markov chain (CMC) model is proposed to analyze the behavior of state machines. It is shown that the feedback loop from the state registers, as well as the state assignments, can adversely affect the characteristics of the patterns generated by the state registers configured as signature analyzers. On the basis of this analysis, there has been developed a new state assignment algorithm that removes the adverse effects of feedback and ensures high controllability. This allows the use of the parallel BIST technique for state machines.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116503986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
The Omnitest system: a no-generate, no-compile, interactive test methodology Omnitest系统:一种无需生成、无需编译的交互式测试方法
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82342
W. Dettloff, Melodie D. Tebbs
{"title":"The Omnitest system: a no-generate, no-compile, interactive test methodology","authors":"W. Dettloff, Melodie D. Tebbs","doi":"10.1109/TEST.1989.82342","DOIUrl":"https://doi.org/10.1109/TEST.1989.82342","url":null,"abstract":"The authors present executable VLSI test software which reads a digital device specification file and dynamically reconfigures the tester at run time. The Omnitest concept has been demonstrated on the Megatest MegaOne VLSI tester. Complete device description files have gone from data manual to error-free-testing in under an hour. The Omnitest program completely masks the detailed operation of the MegaOne, yet allows the user to take advantage of all the tester's sophisticated features. Engineers who have had no previous exposure to test have been able to comprehend and utilize the input language after merely reviewing an example. Besides shortening development times and enabling a high-level approach to digital test, the Omnitest system also frees tester resources, standardizes test-related operations, and provides ample means to revise and amend.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126458536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
FUNTEST: a functional automatic test pattern generator for combinational circuits FUNTEST:用于组合电路的功能自动测试图形生成器
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82397
S. Al-Arian, M. Nordenso
{"title":"FUNTEST: a functional automatic test pattern generator for combinational circuits","authors":"S. Al-Arian, M. Nordenso","doi":"10.1109/TEST.1989.82397","DOIUrl":"https://doi.org/10.1109/TEST.1989.82397","url":null,"abstract":"An automatic test pattern generator (ATPG) for combinational circuits based on a functional description has been developed. The algorithm generates tests on the basis of a set of Boolean equations or higher functional representations where little or no knowledge of the physical structure is required. A functional fault coverage is defined and related to structural fault coverage.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125249276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A military test method for measuring fault coverage 一种用于测量故障覆盖率的军用试验方法
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82402
W. Debany
{"title":"A military test method for measuring fault coverage","authors":"W. Debany","doi":"10.1109/TEST.1989.82402","DOIUrl":"https://doi.org/10.1109/TEST.1989.82402","url":null,"abstract":"Proposed MIL-STD-883 Test Procedure 5012, 'Fault Coverage Measurement for Digital Microcircuits', is described. Numerous fault simulation tools are commercially available; this procedure provides a means of obtaining consistent and repeatable fault coverage values from different fault simulators. The procedure describes requirements governing the development of the logic model for the IC, the assumed fault model and fault universe, fault classing, fault simulation, and fault coverage reporting. It provides a consistent means of reporting fault coverage for an IC regardless of the specific logic and fault simulator used.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128204910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
The pseudoexhaustive test of sequential circuits 顺序电路的伪穷举检验
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82273
S. Hellebrand, H. Wunderlich
{"title":"The pseudoexhaustive test of sequential circuits","authors":"S. Hellebrand, H. Wunderlich","doi":"10.1109/TEST.1989.82273","DOIUrl":"https://doi.org/10.1109/TEST.1989.82273","url":null,"abstract":"The concept of a pseudoexhaustive test for sequential circuits is introduced. Instead of test sets one applies pseudoexhaustive test sequences of a limited length, which provides well-known benefits as far as fault coverage, self-test capability, and simplicity of test generation are concerned. Some flip flops and latches are integrated into an incomplete scan path, such that each possible state of the circuit is reachable within a few steps. Some more flip flops and some new segmentation cells are added to the partial scan path in order to make a pseudoexhaustive test feasible. Algorithms for placing these devices automatically are presented. Also it is shown how to transform a pseudoexhaustive test set into a pseudoexhaustive test sequence of a similar size. The analyzed examples show that a conventional complete scan path without additional testability features requires more hardware overhead than the proposed test strategy, which retains all the known benefits of a pseudoexhaustive test.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128424430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 58
Diagnostics based on faulty signature 基于故障签名的诊断
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82387
J. Chan, B. Womack
{"title":"Diagnostics based on faulty signature","authors":"J. Chan, B. Womack","doi":"10.1109/TEST.1989.82387","DOIUrl":"https://doi.org/10.1109/TEST.1989.82387","url":null,"abstract":"A fault diagnostic algorithm which makes use of the information from a faulty signature is presented. The idea is to search the likely fault locations before the tests are performed. The method reduces the number of tests required to diagnose the faults with the probability of error aliasing. Such probability is always smaller than that of error detection in signature analysis. When matching tests are difficult or impossible, the method provides an estimate of where errors that caused the incorrect signature might have occurred.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130857032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Design and test in the universities 在大学进行设计和测试
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82301
S. Al-Arian
{"title":"Design and test in the universities","authors":"S. Al-Arian","doi":"10.1109/TEST.1989.82301","DOIUrl":"https://doi.org/10.1109/TEST.1989.82301","url":null,"abstract":"It is argued that a broad-based VLSI curriculum should be established in the university. In conjunction with theoretical teaching, facilities that include an integrated design and test environment, CAD tools, and ATE (automatic test equipment) should be provided. A possible program might be directed toward the computer (or electrical) engineering degree with emphasis on VLSI design and testing. The areas that might be included in such a program are design and architecture, device physics and technology, integrated circuits, testing and fault tolerance, CAD tools, algorithms and applications, and processing techniques.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132015389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Methods of test waveform synthesis for high speed data communication devices 高速数据通信设备测试波形合成方法
Proceedings. 'Meeting the Tests of Time'., International Test Conference Pub Date : 1989-08-29 DOI: 10.1109/TEST.1989.82298
K. Lanier
{"title":"Methods of test waveform synthesis for high speed data communication devices","authors":"K. Lanier","doi":"10.1109/TEST.1989.82298","DOIUrl":"https://doi.org/10.1109/TEST.1989.82298","url":null,"abstract":"When testing ISDN (integrated services digital network) and other high-data-rate communications devices, stimulus waveforms will often emulate signals that a device under test (DUT) will process in its final application. When conventionally architected digital-signal-processor-based instrumentation is used to provide these waveforms, there exist test conditions which can easily overburden machine capabilities. The author explores an instrument architecture in use, based on a composite test signal model, which provides for extremely efficient generation of combinational analog/digital test stimuli. This technique is suitable for transmitting extremely long data sequences to DUTs using a hardware modulator scheme which mixes the logical and physical components of a mixed-signal waveform at run time. The limitations of this technique are concerned with to what extent the length of the filter can be implemented; these limitations, however, can be overcome with either additional processing or hardware filters.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132221976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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