The analysis of parallel BIST by the combined Markov chain (CMC) model

Abstract

It is shown that the simple Markov chain model used to define the parallel BIST (built-in self-test) technique (see K. Kim et al., IEEE Trans. CAD Integrated Circuits Syst., p.919-28, Aug. 1988) does not work well for state machines. Instead, a combined Markov chain (CMC) model is proposed to analyze the behavior of state machines. It is shown that the feedback loop from the state registers, as well as the state assignments, can adversely affect the characteristics of the patterns generated by the state registers configured as signature analyzers. On the basis of this analysis, there has been developed a new state assignment algorithm that removes the adverse effects of feedback and ensures high controllability. This allows the use of the parallel BIST technique for state machines.<>