Fault location in repairable programmable logic arrays

Abstract

In order to ensure the manufacture of large PLA (programmable logic array) chips with reasonable yield level, a design for repairable PLAs (RPLAs) was proposed in which the partially defective chips can be repaired without reconfiguring the external routing. However, before a defective chip can be repaired, the locations of the defects must be precisely identified. The author presents a fault location (diagnosis) scheme that achieves a full diagnosability in locating all single and multiple stuck-at, bridging, and crosspoint faults. Two examples are given to demonstrate the proposed scheme.<>