{"title":"A military test method for measuring fault coverage","authors":"W. Debany","doi":"10.1109/TEST.1989.82402","DOIUrl":null,"url":null,"abstract":"Proposed MIL-STD-883 Test Procedure 5012, 'Fault Coverage Measurement for Digital Microcircuits', is described. Numerous fault simulation tools are commercially available; this procedure provides a means of obtaining consistent and repeatable fault coverage values from different fault simulators. The procedure describes requirements governing the development of the logic model for the IC, the assumed fault model and fault universe, fault classing, fault simulation, and fault coverage reporting. It provides a consistent means of reporting fault coverage for an IC regardless of the specific logic and fault simulator used.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TEST.1989.82402","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
Proposed MIL-STD-883 Test Procedure 5012, 'Fault Coverage Measurement for Digital Microcircuits', is described. Numerous fault simulation tools are commercially available; this procedure provides a means of obtaining consistent and repeatable fault coverage values from different fault simulators. The procedure describes requirements governing the development of the logic model for the IC, the assumed fault model and fault universe, fault classing, fault simulation, and fault coverage reporting. It provides a consistent means of reporting fault coverage for an IC regardless of the specific logic and fault simulator used.<>