Cell-based test design method

A cell-based test design method which is consistent with features of cell-based design is introduced. By improving shift register latches, a scan test for asynchronous circuits, as well as delay tests can be executed effectively. Also, by employing a test bus and a selector shift register configuration, a multiple scan-path test is realized attractively, which drastically reduces the execution time of the scan test. This results in the possibility of realizing a hierarchical test design in which the test vectors of module circuits are saved as library data and used in the preparation of the test vector of a newly developed chip and of the schematic and artwork data. It appears that the area overhead and the increase in test time are reasonable for future VLSI chips with the complexity of 1M transistors.<>