{"title":"快速自动故障位分析的dram","authors":"W. Malzfeldt, W. Mohr, H.-D. Oberle, K. Kodalle","doi":"10.1109/TEST.1989.82326","DOIUrl":null,"url":null,"abstract":"Technological failures of DRAMs (dynamic random-access memories) show up in different fault patterns in the failbit map. An automatic program has been developed for testing, fault pattern recognition, classification, and determination of fault class distributions on chips and wafers. The analysis system consists of an ADVANTEST T 3332 memory tester and an ADVANSTAR network with a connection to a remotely located mainframe computer. Selected wafers are tested using the same test conditions as in the production test program in order to reproduce the failbit patterns. The fast automatic failbit analysis was first installed for a 1M DRAM and was later updated for 4M DRAM analysis. Results of the analysis are presented and discussed.<<ETX>>","PeriodicalId":264111,"journal":{"name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"Fast automatic failbit analysis for DRAMs\",\"authors\":\"W. Malzfeldt, W. Mohr, H.-D. Oberle, K. Kodalle\",\"doi\":\"10.1109/TEST.1989.82326\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Technological failures of DRAMs (dynamic random-access memories) show up in different fault patterns in the failbit map. An automatic program has been developed for testing, fault pattern recognition, classification, and determination of fault class distributions on chips and wafers. The analysis system consists of an ADVANTEST T 3332 memory tester and an ADVANSTAR network with a connection to a remotely located mainframe computer. Selected wafers are tested using the same test conditions as in the production test program in order to reproduce the failbit patterns. The fast automatic failbit analysis was first installed for a 1M DRAM and was later updated for 4M DRAM analysis. Results of the analysis are presented and discussed.<<ETX>>\",\"PeriodicalId\":264111,\"journal\":{\"name\":\"Proceedings. 'Meeting the Tests of Time'., International Test Conference\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1989-08-29\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings. 'Meeting the Tests of Time'., International Test Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/TEST.1989.82326\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TEST.1989.82326","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
摘要
动态随机存取存储器(dram)的技术故障在故障位图中表现为不同的故障模式。一个自动程序已开发测试，故障模式识别，分类，并确定故障类分布在芯片和晶圆。分析系统由一个ADVANTEST T 3332存储器测试仪和一个ADVANSTAR网络组成，该网络可连接到远程主机。所选晶圆使用与生产测试程序相同的测试条件进行测试，以重现故障位模式。快速自动故障位分析首先安装在1M DRAM上，后来更新为4M DRAM分析。给出了分析结果并进行了讨论。
Technological failures of DRAMs (dynamic random-access memories) show up in different fault patterns in the failbit map. An automatic program has been developed for testing, fault pattern recognition, classification, and determination of fault class distributions on chips and wafers. The analysis system consists of an ADVANTEST T 3332 memory tester and an ADVANSTAR network with a connection to a remotely located mainframe computer. Selected wafers are tested using the same test conditions as in the production test program in order to reproduce the failbit patterns. The fast automatic failbit analysis was first installed for a 1M DRAM and was later updated for 4M DRAM analysis. Results of the analysis are presented and discussed.<>
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