A sequential circuit fault simulation by surrogate fault propagation

Abstract

A novel technique for synchronous fault simulation of sequential circuits utilizing surrogate fault propagation and backward fault collection is introduced, and its implementation is evaluated. Fault effects which reconverge over time are simulated as exceptions. Evidence which shows SFSSE (synchronous fault simulation by surrogate with exceptions) to be superior to existing approaches is presented. As in deductive and concurrent simulation, execution time drops dramatically as the majority of faults are detected. SFSSE incorporates features of both deductive and parallel fault simulations while avoiding the drawbacks of each of these techniques. In contrast to deductive simulation, fault lists are processed only at primary outputs and memory elements. This is critical with respect to both execution time and storage requirements.<>