2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)最新文献_第2页

A 104.76-TOPS/W, Spike-Based Convolutional Neural Network Accelerator with Reduced On-Chip Memory Data Flow and Operation Unit Skipping 一个104.76-TOPS/W，基于尖峰的卷积神经网络加速器，减少片上存储数据流和操作单元跳变

2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2022-11-11 DOI: 10.1109/APCCAS55924.2022.10090309

P. Huang, Chen-Han Hsu, Yu-Hsiang Cheng, Zhaofang Li, Yu-Hsuan Lin, K. Tang

{"title":"A 104.76-TOPS/W, Spike-Based Convolutional Neural Network Accelerator with Reduced On-Chip Memory Data Flow and Operation Unit Skipping","authors":"P. Huang, Chen-Han Hsu, Yu-Hsiang Cheng, Zhaofang Li, Yu-Hsuan Lin, K. Tang","doi":"10.1109/APCCAS55924.2022.10090309","DOIUrl":"https://doi.org/10.1109/APCCAS55924.2022.10090309","url":null,"abstract":"The energy efficiency of artificial intelligence networks must be increased if they are to be implemented on edge devices. Brain-inspired spiking neural networks (SNNs) are considered potential candidates for this purpose because they do not involve multiplication operations. SNNs only perform addition and shifting operations. SNNs can be used with a convolutional neural network (CNN) to reduce the required computational power. The combination of an SNN and a CNN is called a spiking CNN (SCNN). To achieve a high operation speed with an SCNN, a large memory, which occupies a relatively large area and consumes a relatively large amount of power, is often required. In this paper, a data flow method is proposed to reduce the required on-chip memory and power consumption and to eliminate the operation unit skipping of a high-sparsity SCNN. This method decreases the overall on-chip memory required by an SCNN and increases the network's energy efficiency. When using the proposed method in this study, an SCNN exhibited energy efficiency of 104.76 TOPS/W when processing the CIFA-10 dataset.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"261 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123727929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 12-bit 1 GS/s Current Steering DAC with the Appointed and Thermometer Coding Scheme 一个12位1gs /s电流转向DAC与指定和温度计编码方案

2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2022-11-11 DOI: 10.1109/APCCAS55924.2022.10090369

Ko-Chi Kuo, Ying-Ju Sung

引用次数: 0

A 500-MS/s 9-Bit Time-Domain ADC Using a Nonbinary Successive Approximation TDC 采用非二进制连续逼近TDC的500 ms /s 9位时域ADC

2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2022-11-11 DOI: 10.1109/APCCAS55924.2022.10090395

Yutong Zhao, Fan Ye, Junyan Ren

引用次数: 0

A 0.5 to 2GHz Blocker-Tolerant Receiver Achieving 29dBm OOB-IIP3 and 3.2 to 6dB NF Using Bottom-Plate Switched-Capacitor Technique 采用底板开关电容技术实现29dBm OOB-IIP3和3.2 ~ 6dB NF的0.5 ~ 2GHz容错接收机

2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2022-11-11 DOI: 10.1109/APCCAS55924.2022.10090311

Yi Mao, Yuyang Du, Yongjun He, Gengzhen Qi, Pui-in Mak

引用次数: 0

A Two-stage Training Framework for Hardware Constraints of Computing-in-Memory Architecture 内存计算体系结构硬件约束的两阶段训练框架

2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2022-11-11 DOI: 10.1109/APCCAS55924.2022.10090308

Hao-Wen Kuo, Rui-Hsuan Wang, Zhaofang Li, Shih-Ting Lin, Meng-Fan Chang, K. Tang

{"title":"A Two-stage Training Framework for Hardware Constraints of Computing-in-Memory Architecture","authors":"Hao-Wen Kuo, Rui-Hsuan Wang, Zhaofang Li, Shih-Ting Lin, Meng-Fan Chang, K. Tang","doi":"10.1109/APCCAS55924.2022.10090308","DOIUrl":"https://doi.org/10.1109/APCCAS55924.2022.10090308","url":null,"abstract":"Analog computing-in-memory (CIM) involves high-density interleaved memory arrays beneficial to deep neural networks involving several parallel computations. Furthermore, it displays considerable potential in achieving high energy efficiency in artificial intelligence (AI) accelerators. This work presents a two-stage training framework that considers hardware architecture constraints and analyzes the nonidealities in CIM devices. (1) We designed a CIM convolution algorithm that can be commonly used in various neural networks. (2) In addition, the training framework can quantize weights and activations to their target bit widths and inject noise during the training process to improve the inference robustness of a neural network. In ResNet, our results in Fig. 7 revealed that our framework could improve 2.26% and 8.95% top-1 accuracy on CIFAR-10 and CIFAR-100 without injecting noise. (3) An MVM quantizer offers flexible quantization intervals to the output distribution of each layer for retaining crucial information and enhancing accuracy after the quantization process. The experimental results in Fig. 8 revealed that the accuracy of the ResNet and VGG models increased by 4.48% and 5.46% on CIFAR-10 with traditional linear quantization, respectively. The results of this study demonstrate that the proposed framework is practical and valuable for the fabrication and design of CIM chip systems.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127451794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Pipelined Computing-in-Memory Macro with Computation-Memory Aware Technique 基于计算-内存感知技术的内存中管道计算宏

2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2022-11-11 DOI: 10.1109/APCCAS55924.2022.10090333

L. Chang, Pan Zhao, Jun Zhou

引用次数: 0

A 0.3-μA Quiescent Current Output Capacitor-Less LDO with Dynamic Slew Rate Enhance Buffer 一种0.3 μA无静态电流输出电容的动态摆率增强缓冲LDO

2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2022-11-11 DOI: 10.1109/APCCAS55924.2022.10090347

Tianxiang Wu, Yuting Zhang, Yanhan Zeng

引用次数: 0

Multi-type SRAM Test Structure with an Improved March LR Algorithm 基于改进March LR算法的多类型SRAM测试结构

2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2022-11-11 DOI: 10.1109/APCCAS55924.2022.10090328

Xinshun Ning, Hong-yong Yang, Mengdi Zhang, Yanji Wang, Ye Zhao, Shushan Qiao

引用次数: 0

Achieving < 1% Precision Clocking Solution with External-R under Practical Constraints 在实际约束下用外部r实现< 1%精度的时钟解决方案

2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2022-11-11 DOI: 10.1109/APCCAS55924.2022.10090348

A. Roy, Preetham N. Reddy, N. Agarwal, Nikhil Das

引用次数: 0

A 500-MHz 32-bit DETFF-based Shift Register Utilizing 40-nm CMOS Technology 基于40纳米CMOS技术的500 mhz 32位移位寄存器

2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2022-11-11 DOI: 10.1109/APCCAS55924.2022.10090380

Jyoshnavi Akiri, L. K. Tolentino, L. Yang, B. Esakki, S. Sampath, Chua-Chin Wang

引用次数: 0