Pipelined Computing-in-Memory Macro with Computation-Memory Aware Technique

Abstract

Computing-in-Memory (CIM) architecture is suitable for artificial intelligent accelerators, where frequent data movements are required between computation and memory units. CIM-based processing engine reduces redundant data interaction by integrated computation in/with memory and has become a promising candidate to alternate traditional multiply-and-accumulator (MAC). However, most of the previous CIM macros only considered computation without concern for the memory attribute, leading to a low memory computing ratio. This paper presents an SRAM-based digital CIM macro supporting pipeline mode and computation-memory aware technique to improve the ratio of memory-computation. We develop a novel weight driver with fine-grained ping-pong operation, avoiding the computation halt caused by weight updating. Based on our evaluation, the peak energy efficiency is 19.78TOPS/W at 22 nm technology node, 8-bit width, and 50% sparsity of input feature map.