{"title":"Achieving < 1% Precision Clocking Solution with External-R under Practical Constraints","authors":"A. Roy, Preetham N. Reddy, N. Agarwal, Nikhil Das","doi":"10.1109/APCCAS55924.2022.10090348","DOIUrl":null,"url":null,"abstract":"An external resistor $(R_{EXT})$ based clocking solution with $< 1\\%$ precision is presented in this paper. Though $R_{EXT}$ can have much better temperature coefficient (TC), e.g. TCl $=25\\text{ppm}/^{\\circ}\\mathrm{C}$ and negligible TC2, practical considerations in an integrated system-on-chip (SoC), such as micro-controller (MCU) opposes the benefits. For low cost SoCs, it is desired that the EXTR-pin (i.e. the pin where $R_{EXT}$ is mounted) shares a general purpose I/O pin (GPIO). Under this constraint, adjacent GPIO switching can cause significant coupling onto EXTR-pin resulting in intolerable jitter. Additionally, the shared, tri-stated GPIO adds leakage current with nonlinear temperature profile, into $R_{EXT}$ causing curvature error in frequency. These are solved by novel circuit solutions which finally help achieve the targeted precision. Measured and simulated results are provided to support the claims.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APCCAS55924.2022.10090348","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
An external resistor $(R_{EXT})$ based clocking solution with $< 1\%$ precision is presented in this paper. Though $R_{EXT}$ can have much better temperature coefficient (TC), e.g. TCl $=25\text{ppm}/^{\circ}\mathrm{C}$ and negligible TC2, practical considerations in an integrated system-on-chip (SoC), such as micro-controller (MCU) opposes the benefits. For low cost SoCs, it is desired that the EXTR-pin (i.e. the pin where $R_{EXT}$ is mounted) shares a general purpose I/O pin (GPIO). Under this constraint, adjacent GPIO switching can cause significant coupling onto EXTR-pin resulting in intolerable jitter. Additionally, the shared, tri-stated GPIO adds leakage current with nonlinear temperature profile, into $R_{EXT}$ causing curvature error in frequency. These are solved by novel circuit solutions which finally help achieve the targeted precision. Measured and simulated results are provided to support the claims.