A Two-stage Training Framework for Hardware Constraints of Computing-in-Memory Architecture

Abstract

Analog computing-in-memory (CIM) involves high-density interleaved memory arrays beneficial to deep neural networks involving several parallel computations. Furthermore, it displays considerable potential in achieving high energy efficiency in artificial intelligence (AI) accelerators. This work presents a two-stage training framework that considers hardware architecture constraints and analyzes the nonidealities in CIM devices. (1) We designed a CIM convolution algorithm that can be commonly used in various neural networks. (2) In addition, the training framework can quantize weights and activations to their target bit widths and inject noise during the training process to improve the inference robustness of a neural network. In ResNet, our results in Fig. 7 revealed that our framework could improve 2.26% and 8.95% top-1 accuracy on CIFAR-10 and CIFAR-100 without injecting noise. (3) An MVM quantizer offers flexible quantization intervals to the output distribution of each layer for retaining crucial information and enhancing accuracy after the quantization process. The experimental results in Fig. 8 revealed that the accuracy of the ResNet and VGG models increased by 4.48% and 5.46% on CIFAR-10 with traditional linear quantization, respectively. The results of this study demonstrate that the proposed framework is practical and valuable for the fabrication and design of CIM chip systems.