A 0.5 to 2GHz Blocker-Tolerant Receiver Achieving 29dBm OOB-IIP3 and 3.2 to 6dB NF Using Bottom-Plate Switched-Capacitor Technique

Abstract

In this paper, a blocker-tolerant receiver (RX) is proposed covering 0.5 to 2GHz, which incorporates a gain-boosted (GB) mixer-first low-noise amplifier (LNA) network and a bottom-plate switched-capacitor (SC) N-path filter to enhance the out-of-band (OOB) blocker suppression and also improve the noise figure (NF). Furthermore, a clock-delay technique is proposed to improve the LO non-overlap characteristics. Implemented in 65nm CMOS technology, the simulated results present that under 80MHz offset frequency the RX achieves 29dBm OOB-IIP3 and −2.3dBm B −1dB. The noise figure (NF) is simulated ranging from 3.2 to 6dB, and the active area is 0.66mm2. At 2GHz, the power consumption is 25mW, in which only 4.7mW is due to the LO dynamic power.