2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)最新文献_第10页

A Booth-based Digital Compute-in-Memory Marco for Processing Transformer Model 基于展台的数字内存计算Marco处理变压器模型

2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2022-11-11 DOI: 10.1109/APCCAS55924.2022.10090256

Zhongyuan Feng, Bo Wang, Zhaoyang Zhang, An Guo, Xin Si

引用次数: 0

FPGA Implementation of Matrix Decomposition Based FIR Filter 基于矩阵分解的FIR滤波器的FPGA实现

2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2022-11-11 DOI: 10.1109/APCCAS55924.2022.10090350

Hao Wang, Jia Yan

引用次数: 0

Hierarchical DNN with Heterogeneous Computing Enabled High-Performance DNA Sequencing 层次DNN与异构计算支持高性能DNA测序

2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2022-11-11 DOI: 10.1109/APCCAS55924.2022.10090281

Shaobo Luo, Zhiyuan Xie, Gengxin Chen, Lei Cui, Mei Yan, Xiwei Huang, Shuwei Li, Changhai Man, Wei Mao, Hao Yu

{"title":"Hierarchical DNN with Heterogeneous Computing Enabled High-Performance DNA Sequencing","authors":"Shaobo Luo, Zhiyuan Xie, Gengxin Chen, Lei Cui, Mei Yan, Xiwei Huang, Shuwei Li, Changhai Man, Wei Mao, Hao Yu","doi":"10.1109/APCCAS55924.2022.10090281","DOIUrl":"https://doi.org/10.1109/APCCAS55924.2022.10090281","url":null,"abstract":"DNA sequencing is a popular tool to demystify the code of living organisms and is reforming the medical, pharmaceutical and biotech industries. The Next-Generation Sequencing (NGS) plays a vital role in high-throughput DNA sequencing with massively parallel data generation. Nevertheless, the massive amount of data imposes great challenges for data analysis. It is arduous to reach a low error rate for handling noisy and/or biased signals owing to the imperfect biochemical reactions and imaging systems. Furthermore, a homogeneous computing system lacks computing power and memory bandwidth. Therefore, in this work, a heterogeneous computing platform with a hierarchical deep neural network sequencing pipeline is proposed to improve the sequencing quality and increase processing speed. Experiments demonstrate that the proposed work reached higher effective throughput (12.18% more clusters found), lower error rate (0.0175%), higher quality score (%Q30 99.27%), and 19% faster. The reported work empowers virus detection, diseases diagnostic, and other potential biomedical applications.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129551161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An Energy-Efficient Mixed-Bit ReRAM-based Computing-in-Memory CNN Accelerator with Fully Parallel Readout 基于全并行读出的高效混合位内存计算CNN加速器

2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2022-11-11 DOI: 10.1109/APCCAS55924.2022.10090365

Dingbang Liu, Wei Mao, Haoxiang Zhou, Jun Liu, Qiuping Wu, Haiqiao Hong, Hao Yu

{"title":"An Energy-Efficient Mixed-Bit ReRAM-based Computing-in-Memory CNN Accelerator with Fully Parallel Readout","authors":"Dingbang Liu, Wei Mao, Haoxiang Zhou, Jun Liu, Qiuping Wu, Haiqiao Hong, Hao Yu","doi":"10.1109/APCCAS55924.2022.10090365","DOIUrl":"https://doi.org/10.1109/APCCAS55924.2022.10090365","url":null,"abstract":"Computing-In-memory (CIM) accelerators have the characteristics of storage and computing integration, which has the potential to break through the limit of Moore's law and the bottleneck of Von-Neumann architecture. However, the performance of CIM accelerators is still limited by conventional CNN architectures and inefficient readouts. To increase energy-efficient performance, optimized CNN model is required and low-power fully parallel readout is necessary for edge-computing hardware. In this work, an ReRAM-based CNN accelerator is designed. Mixed-bit 1~8-bit operations are supported by bitwidth configuration scheme for implementing Neural Architecture Search (NAS)-optimized multi-bit CNNs. Besides, energy-efficient fully parallel readout is achieved by variation-reduction accumulation mechanism and low-power readout circuits. Benchmarks show that the proposed ReRAM accelerator can achieve peak energy efficiency of 2490.32 TOPS/W for 1-bit operation and average energy efficiency of 479.37 TOPS/W for 1~8-bit operations when evaluating NAS-optimized multi-bitwidth CNNs.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"55 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113939342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Hierarchical and Recursive Floorplanning Algorithm for NoC-Bascd Scalable Multi-Die FPGAs 基于noc的可扩展多模fpga分层递归布局算法

2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2022-11-11 DOI: 10.1109/APCCAS55924.2022.10090338

Jianwen Luo, Xinzhe Liu, Fupeng Chen, Y. Ha

{"title":"Hierarchical and Recursive Floorplanning Algorithm for NoC-Bascd Scalable Multi-Die FPGAs","authors":"Jianwen Luo, Xinzhe Liu, Fupeng Chen, Y. Ha","doi":"10.1109/APCCAS55924.2022.10090338","DOIUrl":"https://doi.org/10.1109/APCCAS55924.2022.10090338","url":null,"abstract":"Emerging applications are calling for significantly larger FPGAs with multi-dies. However, these multi-die FPGAs with a traditional substrate-based interconnection are not scalable enough, because the execution time and probability of failure of their floorplanning algorithm will increase dramatically with the growth of design or the number of ides. Therefore, future multi-die FPGAs will require a scalable interconnection architecture and its associated floorplanning algorithm. To address this issue, we propose both a new NoC-based scalable multi-die FPGA architecture and a corresponding floorplanning algorithm, namely Hierarchical and Recursive Floorplanning Algorithm(HRFA). First, we introduce the interconnection architecture with a class of scalable hierarchical topologies. Second, we formulate the floorplanning problem for the proposed NoC architecture as an ILP (Integer Linear Programming). Third, we develop a novel recursive method to solve the ILP formulation by taking advantage of the parallelization opportunities exploited from the hierarchical interconnection architectures. The experiments on a Convolutional Neural Network (CNN) benchmark show that the scalability of our proposed technique is at least $3times$ as that of the state-of-the-art solutions measured by the size of the feasible benchmark, with no loss of design performance.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125169773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Chaotic Sampling of Double Scroll Chaos for Digital Random Number Generation 用于数字随机数生成的双涡旋混沌混沌采样

2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2022-11-11 DOI: 10.1109/APCCAS55924.2022.10090396

Onur Karatas, Kaya Demir, Salih Ergün

引用次数: 0

An Approximate-Computing-Based Adaptive Equalizer for Polarization Mode Dispersion 基于近似计算的偏振模色散自适应均衡器

2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2022-11-11 DOI: 10.1109/APCCAS55924.2022.10090404

Liyu Lin, Junhui Wang, Xiaoyang Zeng, Yun Chen

引用次数: 0

The Synergetic Effects of Total Ionizing Dose and High Temperature on 180 nm DSOI Technology 总电离剂量和高温对180nm DSOI工艺的协同效应

2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2022-11-11 DOI: 10.1109/APCCAS55924.2022.10090371

Xu Zhang, Fanyu Liu, Bo Li, Siyuan Chen, Yang Huang, Jiangjiang Li, J. Jiao, T. Ye, Jiajun Luo

{"title":"The Synergetic Effects of Total Ionizing Dose and High Temperature on 180 nm DSOI Technology","authors":"Xu Zhang, Fanyu Liu, Bo Li, Siyuan Chen, Yang Huang, Jiangjiang Li, J. Jiao, T. Ye, Jiajun Luo","doi":"10.1109/APCCAS55924.2022.10090371","DOIUrl":"https://doi.org/10.1109/APCCAS55924.2022.10090371","url":null,"abstract":"The synergetic effects of high temperature and total ionizing dose effects of H-gate DSOI are investigated under the TG-state bias condition. The comparative irradiation experiments are subjected to identify the synergetic effects by separating pure-temperature and pure-irradiation effects. Furthermore, the mitigated TID responses with/without back-gate compensation are discussed. The results show that synergetic effects make threshold voltage degradation weaken for our devices with the $boldsymbol{V}_{text{SO12}}=0 mathbf{V}$ during testing. It can be explained that the electrons will be more likely to tunnel into the oxides and compensate the trapped charges with temperature rising. Besides, with the $boldsymbol{V}_{text{SO}12}=-boldsymbol{10} mathrm{V}$, the common TID mitigation was observed under room temperature and the synergetic effects can still be greatly compensated due to the electric field lines induced by positive trapped charges terminating into the negatively biased electrode. It may enlighten us the high TID tolerance of DSOI can be achieved in very harsh environments.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115982599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

High-Speed and Low-Complexity Modular Reduction Design for CRYSTALS-Kyber CRYSTALS-Kyber的高速低复杂度模块化简化设计

2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2022-11-11 DOI: 10.1109/APCCAS55924.2022.10090253

Minghao Lil, Jing Tian, Xiao Hu, Yuan Cao, Zhongfeng Wang

引用次数: 1

A 50-Gb/s NRZ Receiver Targeting Low-Latency Multi-Chip Module Optical I/O in 45-nm SOI CMOS 基于45nm SOI CMOS的50gb /s低延迟多芯片模块光I/O NRZ接收器

2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2022-11-11 DOI: 10.1109/APCCAS55924.2022.10090261

Yihong Li, Sikai Chen, Yunqi Yang, Qianli Ma, Ming Zhong, Ziyi Lin, Leliang Li, Guike Li, Zhao Zhang, Liyuan Liu, Jian Liu, N. Wu, Yong Chen, Qi Peng, Nan Qi

引用次数: 1