FPGA Implementation of Matrix Decomposition Based FIR Filter

Abstract

Matrix decomposition (MD) based finite impulse response filter (FIR) can synthesize any FIR filter with much fewer coefficients, without affecting the group delay and only scarcely affecting the frequency domain design error. Several researchers have advanced the theoretical analysis of a MD-FIR filter since it is first proposed. As the previous research is all about the theoretical analysis, this study presents the FPGA implementation of MD-FIR filters for the first time. First, a continuous coefficient MD-FIR filter is designed by using the well-developed method. Then, this MD-FIR filter is implemented in Matlab Simulink. Afterwards, the Verilog code for implementing a MD-FIR filter is automatically generated based on the Matlab Simulink implementation. Finally, based on the Verilog code, the MD-FIR filter is simulated and implemented in Field Programmable Gate Arrays (FPGA). The results verify the effectiveness of a MD-FIR filter.