{"title":"基于矩阵分解的FIR滤波器的FPGA实现","authors":"Hao Wang, Jia Yan","doi":"10.1109/APCCAS55924.2022.10090350","DOIUrl":null,"url":null,"abstract":"Matrix decomposition (MD) based finite impulse response filter (FIR) can synthesize any FIR filter with much fewer coefficients, without affecting the group delay and only scarcely affecting the frequency domain design error. Several researchers have advanced the theoretical analysis of a MD-FIR filter since it is first proposed. As the previous research is all about the theoretical analysis, this study presents the FPGA implementation of MD-FIR filters for the first time. First, a continuous coefficient MD-FIR filter is designed by using the well-developed method. Then, this MD-FIR filter is implemented in Matlab Simulink. Afterwards, the Verilog code for implementing a MD-FIR filter is automatically generated based on the Matlab Simulink implementation. Finally, based on the Verilog code, the MD-FIR filter is simulated and implemented in Field Programmable Gate Arrays (FPGA). The results verify the effectiveness of a MD-FIR filter.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"1891 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"FPGA Implementation of Matrix Decomposition Based FIR Filter\",\"authors\":\"Hao Wang, Jia Yan\",\"doi\":\"10.1109/APCCAS55924.2022.10090350\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Matrix decomposition (MD) based finite impulse response filter (FIR) can synthesize any FIR filter with much fewer coefficients, without affecting the group delay and only scarcely affecting the frequency domain design error. Several researchers have advanced the theoretical analysis of a MD-FIR filter since it is first proposed. As the previous research is all about the theoretical analysis, this study presents the FPGA implementation of MD-FIR filters for the first time. First, a continuous coefficient MD-FIR filter is designed by using the well-developed method. Then, this MD-FIR filter is implemented in Matlab Simulink. Afterwards, the Verilog code for implementing a MD-FIR filter is automatically generated based on the Matlab Simulink implementation. Finally, based on the Verilog code, the MD-FIR filter is simulated and implemented in Field Programmable Gate Arrays (FPGA). The results verify the effectiveness of a MD-FIR filter.\",\"PeriodicalId\":243739,\"journal\":{\"name\":\"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)\",\"volume\":\"1891 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-11-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/APCCAS55924.2022.10090350\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APCCAS55924.2022.10090350","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
FPGA Implementation of Matrix Decomposition Based FIR Filter
Matrix decomposition (MD) based finite impulse response filter (FIR) can synthesize any FIR filter with much fewer coefficients, without affecting the group delay and only scarcely affecting the frequency domain design error. Several researchers have advanced the theoretical analysis of a MD-FIR filter since it is first proposed. As the previous research is all about the theoretical analysis, this study presents the FPGA implementation of MD-FIR filters for the first time. First, a continuous coefficient MD-FIR filter is designed by using the well-developed method. Then, this MD-FIR filter is implemented in Matlab Simulink. Afterwards, the Verilog code for implementing a MD-FIR filter is automatically generated based on the Matlab Simulink implementation. Finally, based on the Verilog code, the MD-FIR filter is simulated and implemented in Field Programmable Gate Arrays (FPGA). The results verify the effectiveness of a MD-FIR filter.