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2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)最新文献

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Autoencoder-Based Anomaly Detection for Time Series Data in Complex Systems 基于自编码器的复杂系统时间序列数据异常检测
2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2022-11-11 DOI: 10.1109/APCCAS55924.2022.10090260
Xundong Gong, Shibo Liao, Fei Hu, Xiaoqing Hu, Chunshan Liu
{"title":"Autoencoder-Based Anomaly Detection for Time Series Data in Complex Systems","authors":"Xundong Gong, Shibo Liao, Fei Hu, Xiaoqing Hu, Chunshan Liu","doi":"10.1109/APCCAS55924.2022.10090260","DOIUrl":"https://doi.org/10.1109/APCCAS55924.2022.10090260","url":null,"abstract":"In this paper, we present a new anomaly detection method for time-series data in complex systems such as power grid and cellular networks. The proposed anomaly detection method is developed following unsupervised learning, where an AutoEncoder based on Gated Recurrent Units (GRU-AE) is trained to reconstruct a time-series of interest, and anomalies are detected via detecting exceptionally large reconstruction errors. A multi-timestamp stacking method is adopted to reduce the number of time steps in the GRU-AE to facilitate the training of the model and a new training scheme with random shuffling is proposed to prevent overfitting. The proposed GRU-AE based detector is applied in multiple time scales to detect different types of anomalies. Numerical results obtained via time-series data from real cellular network demonstrate the performance of the proposed method.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116746563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design of Integrated Circuit Hard Defect Location System Based on Thermal Laser Stimulation 基于热激光刺激的集成电路硬缺陷定位系统设计
2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2022-11-11 DOI: 10.1109/APCCAS55924.2022.10090341
Wenjian Wu, Yingqi Ma, Minghui Cai
{"title":"Design of Integrated Circuit Hard Defect Location System Based on Thermal Laser Stimulation","authors":"Wenjian Wu, Yingqi Ma, Minghui Cai","doi":"10.1109/APCCAS55924.2022.10090341","DOIUrl":"https://doi.org/10.1109/APCCAS55924.2022.10090341","url":null,"abstract":"Locating the fault position through the test system is a crucial part of the failure mechanism analysis of an integrated circuit. This paper presents a scanning and location system to detect integrated circuit hard defects based on Thermal Laser Stimulation (TLS) technology. The system uses a near-infrared laser to irradiate the device by planar scanning to obtain the current/voltage scan variation data of the sample. Then it can show the position of the failure point of the sample based on the abnormal distribution of the number of electrical parameter changes. Scan mode contains fast and slow scan modes for balancing test efficiency and reliability. The current signal during laser irradiation is mainly composed of Optical Beam Induced Resistance Change (OBIRCH) signal and Seebeck Effect (SE) signal. SE signal will act like noise and affect the OBIRCH signal continuously. The system can eliminate the interference of the SE signal by testing the signal separately and then subtracting it from the mixed signal at the test points. The experimental results show that the system can well locate hard defects of integrated circuits.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114269931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Nanowatt High Order Analog Fully-Differential Bandpass Filter with Passive Switched-Capacitor Circuits 带无源开关电容电路的纳瓦高阶模拟全差分带通滤波器
2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2022-11-11 DOI: 10.1109/APCCAS55924.2022.10090382
Shiying Zhang, Xian Tang
{"title":"Nanowatt High Order Analog Fully-Differential Bandpass Filter with Passive Switched-Capacitor Circuits","authors":"Shiying Zhang, Xian Tang","doi":"10.1109/APCCAS55924.2022.10090382","DOIUrl":"https://doi.org/10.1109/APCCAS55924.2022.10090382","url":null,"abstract":"This paper presents a kind of high order analog fully-differential bandpass filter based on passive switched-capacitor circuits. It can be widely used in many systems, such as voice feature extraction in voice activity detection and keyword spotter. By raising the thought of combining zero generation stages and pole generation stages rather than building stages separately in traditional ways, power consumption can be quite decreased. The power consumption of our filter bank composed of eight filters is 77.98nW in 180-nm CMOS. To analyze the bandpass filter theoretically, we use two methods both in z-domain and with its equivalent circuit. Besides, some effective improvements of switches and clocks are adopted for better performance, showing the result of $boldsymbol{10.85}mu mathrm{V}_{text{rms}}$ output-referred noise and 71.ldB dynamic range at 5% THD, having the advantages over other bandpass filters with similar functions.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126716504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 0.006-mm26-to-20-Gb/s NRZ Bang-Bang Clock and Data Recovery Circuit With Dual-Path Loop 一种0.006-mm26- 20gb /s的双径环NRZ Bang-Bang时钟和数据恢复电路
2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2022-11-11 DOI: 10.1109/APCCAS55924.2022.10090393
Zhao Zhang, Xinyu Shen, Yixi Li, Guike Li, Nan Qi, Jian Liu, N. Wu, Liyuan Liu, Yong Chen, Zhao Zhang
{"title":"A 0.006-mm26-to-20-Gb/s NRZ Bang-Bang Clock and Data Recovery Circuit With Dual-Path Loop","authors":"Zhao Zhang, Xinyu Shen, Yixi Li, Guike Li, Nan Qi, Jian Liu, N. Wu, Liyuan Liu, Yong Chen, Zhao Zhang","doi":"10.1109/APCCAS55924.2022.10090393","DOIUrl":"https://doi.org/10.1109/APCCAS55924.2022.10090393","url":null,"abstract":"This paper presents a compact broad-bandwidth dual-path loop clock and data recovery (CDR) circuit with a low jitter to support the non-return-to-zero (NRZ). A charge-sharing integrator is adapted in the I-path to decrease the step size of frequency adjustment for the low jitter of the recovered clock while maintaining a small I-path capacitor. Designed in a 40-nm CMOS process, our CDR can operate from 6 Gb/s to 20 Gb/s while only occupying a core active area of 0.00612 mm2, The simulation results indicate that the proposed CDR achieves 0.573-psrms recovered clock jitter with a 7.7-mW power at 20Gb/s.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128918356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Hardware-Aware Quantization for Multiplierless Neural Network Controllers 无乘法器神经网络控制器的硬件感知量化
2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2022-11-11 DOI: 10.1109/APCCAS55924.2022.10090271
Tobias Habermann, Jonas Kühle, M. Kumm, Anastasia Volkova
{"title":"Hardware-Aware Quantization for Multiplierless Neural Network Controllers","authors":"Tobias Habermann, Jonas Kühle, M. Kumm, Anastasia Volkova","doi":"10.1109/APCCAS55924.2022.10090271","DOIUrl":"https://doi.org/10.1109/APCCAS55924.2022.10090271","url":null,"abstract":"Deep neural networks (DNNs) have been successfully applied to the approximation of non-linear control systems. These DNNs, deployed in safety-critical embedded systems, are relatively small but require a high throughput. Our goal is to perform a coefficient quantization to reduce the arithmetic complexity while maintaining an inference with high numerical accuracy. The key idea is to target multiplierless parallel architectures, where constant multiplications are replaced by bit-shifts and additions. We propose an adder-aware training that finds the quantized fixed-point coefficients minimizing the number of adders and thus improving the area, latency and power. With this approach, we demonstrate that an automatic cruise control floating-point DNN can be retrained to have only power-of-two coefficients, while maintaining a similar mean squared error (MSE) and formally satisfying a safety check. We provide a push-button training and implementation framework, automatically generating the VHDL code.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"93 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129404807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Design and Implementation of a Low Power Switched-Capacitor-Based Analog Feature Extractor for Voice Keyword Spotting 基于开关电容的低功耗语音关键字模拟特征提取器的设计与实现
2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2022-11-11 DOI: 10.1109/APCCAS55924.2022.10090360
Feifei Chen, Ka-Fai Un, Wei-Han Yu, Pui-in Mak, R. Martins
{"title":"Design and Implementation of a Low Power Switched-Capacitor-Based Analog Feature Extractor for Voice Keyword Spotting","authors":"Feifei Chen, Ka-Fai Un, Wei-Han Yu, Pui-in Mak, R. Martins","doi":"10.1109/APCCAS55924.2022.10090360","DOIUrl":"https://doi.org/10.1109/APCCAS55924.2022.10090360","url":null,"abstract":"A low-power keyword spotting (KWS) is demanding for the smart human-device interface. The conventional analog feature extractor utilizes an analog filter bank that consumes large power and area. This paper presents a KWS with a low-power switched-capacitor-based feature extractor. The feature extractor employs two pipelining time-domain convolutional neural networks (TD-CNNs) to extract sufficient features for KWS. The TD-CNNs utilize sparsity aware computation (SAC) and sparsified quantization (SQ) for a 4-bit weight quantization. The features are quantized to 2-bit for further classification by an off-chip deep neural network. The analog feature extractor is designed in a 55-nm CMOS process and post-layout simulation is provided. It consumes 4.4 µW at a 1.2-V power supply, with an area of 0.39 mm2. It achieves an accuracy of 92.2% for the google command dataset (GSCD) with five classes.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132858872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low Power and High Speed Designs of CIC Filter for Sigma-Delta ADCs Sigma-Delta模数转换器的低功耗高速CIC滤波器设计
2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2022-11-11 DOI: 10.1109/APCCAS55924.2022.10090324
Zhikun He, Xinpeng Xing, Xinfa Zheng, Haigang Feng, H. Fu, G. Gielen
{"title":"Low Power and High Speed Designs of CIC Filter for Sigma-Delta ADCs","authors":"Zhikun He, Xinpeng Xing, Xinfa Zheng, Haigang Feng, H. Fu, G. Gielen","doi":"10.1109/APCCAS55924.2022.10090324","DOIUrl":"https://doi.org/10.1109/APCCAS55924.2022.10090324","url":null,"abstract":"Cascaded integrator-comb (CIC) filter is widely used as the first stage of decimation filter in Sigma-Delta ADC due to its simple structure and high operation frequency. This paper mainly consists of two works. First, aiming at the power consumption bottleneck, an improved hybrid CIC filter with 625MHz working frequency, 3bits input, 4-level cascade and extraction multiple of 8 is designed in 28nm CMOS. Second, aiming at the speed limitation, a non-recursive CIC filter with 2GHz operating frequency, 3bits input, 4-level cascade and 8 extraction multiple is optimized by extraction multiple allocation strategy in 28nm CMOS. The results of placement and routing (PR) show that under the same frequency, the 0.2607mW power of the hybrid structure CIC filter is reduced by 41.69% compared with traditional recursive structure, and its area is increased by 10.8%. The non-recursive CIC filter can reach 2GHz frequency, with power consumption of 0.9493mW. Compared with the traditional recursive structure, the speed is increased by 3.2 times, and the area is increased by 5.33%.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130461241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 4-Vppd160-Gb/s PAM-4 Optical Modulator Driver with All-Pass Filter-Based Dynamic Bias and 2- Tap FFE in 130-nm BiCMOS 基于全通滤波器动态偏置和2分路FFE的4-Vppd160-Gb/s PAM-4光调制器驱动
2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2022-11-11 DOI: 10.1109/APCCAS55924.2022.10090363
Shuo Feng, Fuzhan Chen, Zhenghao Li, Wentao Zhou, Dongfan Xu, Chun-Zhang Chen, Xuhui Liu, Hanming Wu, Quan Pan
{"title":"A 4-Vppd160-Gb/s PAM-4 Optical Modulator Driver with All-Pass Filter-Based Dynamic Bias and 2- Tap FFE in 130-nm BiCMOS","authors":"Shuo Feng, Fuzhan Chen, Zhenghao Li, Wentao Zhou, Dongfan Xu, Chun-Zhang Chen, Xuhui Liu, Hanming Wu, Quan Pan","doi":"10.1109/APCCAS55924.2022.10090363","DOIUrl":"https://doi.org/10.1109/APCCAS55924.2022.10090363","url":null,"abstract":"This paper presents a high-speed, large-output swing driver with 2-tap feed-forward equalizer (FFE) for optical modulators in 130-nm SiGe BiCMOS process. A breakdown voltage (BV) doubler topology with all-pass filter (APF)-based dynamic bias is applied in the driver to improve the output swing and the bandwidth. A 2-tap fractional-spaced FFE is implemented to compensate for the insufficient bandwidth of optical modulators. Simulation results indicate that the driver achieves an output swing of 4 $mathrm{v}_{text{ppd}}$ and a 3-dB bandwidth of 62.4 GHz with a power consumption of 1.15 W. The performance of the driver is further evaluated in an electrical/optical (E/O) system where a Verilog-A model for Mach-Zehnder Modulator (MZM) with a 3-dB bandwidth of 35 GHz is used. Taking advantages of the 2-tap FFE, the E/O system achieves a 3-dB bandwidth of 50.4 GHz and can support 160-Gb/s PAM-4 optical communications.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131350316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 1.93TOPS/W Deep Learning Processor with a Reconfigurable Processing Element Array Based on SRAM Access Optimization 基于SRAM访问优化的可重构处理单元阵列1.93TOPS/W深度学习处理器
2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2022-11-11 DOI: 10.1109/APCCAS55924.2022.10090334
Liao-Chuan Chen, Zhaofang Li, Yi-Jhen Lin, Kuang Lee, K. Tang
{"title":"A 1.93TOPS/W Deep Learning Processor with a Reconfigurable Processing Element Array Based on SRAM Access Optimization","authors":"Liao-Chuan Chen, Zhaofang Li, Yi-Jhen Lin, Kuang Lee, K. Tang","doi":"10.1109/APCCAS55924.2022.10090334","DOIUrl":"https://doi.org/10.1109/APCCAS55924.2022.10090334","url":null,"abstract":"Deep convolutional neural networks feature numerous parameters, causing data movement to usually dominate the power consumed when computing inferences. This paper proposes an on-chip buffer access optimization method and high-data-reuse architecture that can reduce the power consumed by an on-chip buffer by up to 67.8%. The chip is designed in a TSMC 40 nm process running at 200 MHz and achieves energy efficiency of 1.93 TOPS/W.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"2002 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131386571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Implementation of a Training Computer Program for Circuit Analysis in the Time Domain 时域电路分析训练计算机程序的实现
2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2022-11-11 DOI: 10.1109/APCCAS55924.2022.10090378
A. Kornilov
{"title":"Implementation of a Training Computer Program for Circuit Analysis in the Time Domain","authors":"A. Kornilov","doi":"10.1109/APCCAS55924.2022.10090378","DOIUrl":"https://doi.org/10.1109/APCCAS55924.2022.10090378","url":null,"abstract":"Various programs are used in teaching electrical engineering. Both mathematical support programs and full-fledged electrical circuit simulators are used. At the initial stage, it is important to give the student a clear and simple tool that will allow them to master the basics of electrical engineering. A small program for circuit analysis in the time domain is proposed as such a tool. The theory of methods of analysis and numerical integration underlying the program code is explained. Using the example of an electric circuit, the procedure for working with the program is explained.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"153 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134155486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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