A 0.006-mm26-to-20-Gb/s NRZ Bang-Bang Clock and Data Recovery Circuit With Dual-Path Loop

This paper presents a compact broad-bandwidth dual-path loop clock and data recovery (CDR) circuit with a low jitter to support the non-return-to-zero (NRZ). A charge-sharing integrator is adapted in the I-path to decrease the step size of frequency adjustment for the low jitter of the recovered clock while maintaining a small I-path capacitor. Designed in a 40-nm CMOS process, our CDR can operate from 6 Gb/s to 20 Gb/s while only occupying a core active area of 0.00612 mm2, The simulation results indicate that the proposed CDR achieves 0.573-psrms recovered clock jitter with a 7.7-mW power at 20Gb/s.