2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)最新文献

筛选
英文 中文
Thermometer Code of Log Mel-Frequency Spectral Coefficient for BNN-based Keyword Spotting System Log mel温度计代码-基于bnn的关键词识别系统的频谱系数
2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2022-11-11 DOI: 10.1109/APCCAS55924.2022.10090286
Yuzhong Jiao, Yiu Kei Li, C. Chan, Yun Li, Zhilin Ai
{"title":"Thermometer Code of Log Mel-Frequency Spectral Coefficient for BNN-based Keyword Spotting System","authors":"Yuzhong Jiao, Yiu Kei Li, C. Chan, Yun Li, Zhilin Ai","doi":"10.1109/APCCAS55924.2022.10090286","DOIUrl":"https://doi.org/10.1109/APCCAS55924.2022.10090286","url":null,"abstract":"For keyword spotting (KWS) systems that usually work in mobile devices, a low-complexity design is essential for long stand-by time. Audio feature extraction and classifier modeling are the two main components of KWS systems. Log Mel-Frequency Spectral Coefficient (MFSC) is common for audio feature extraction due to its low complexity and good performance. Binary neural network (BNN) classifier, which owns binary weights and activations and performs convolution with XNOR, is applicable to low-complexity KWS applications. However, audio features are usually quantized with multiple-bit binary code to maintain high classification accuracy, which requires addition (ADD) operations in the first convolutional layer of the BNN model. Therefore, both XNOR and ADD units are needed in the BNN accelerator. To further reduce the complexity of KWS systems, we propose a new feature extraction method: Thermometer Codes of MFSC (MFSC-TC). Without LOG and DELTA operations, it is simpler than other MFSC-based methods. More importantly, convolution of all layers can be done by XNOR units due to the feature of thermometer code. The experiments with the Google Speech Commands dataset validate that the MFSC-TC-based BNN models outperform the models with more layers using other feature extraction methods.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114330286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Change Point Detection for Time Series Data in Complex Systems 复杂系统中时间序列数据的变化点检测
2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2022-11-11 DOI: 10.1109/APCCAS55924.2022.10090392
Xundong Gong, Jia Ma, Ming Chen, Shaolei Zong, Chunshan Liu
{"title":"Change Point Detection for Time Series Data in Complex Systems","authors":"Xundong Gong, Jia Ma, Ming Chen, Shaolei Zong, Chunshan Liu","doi":"10.1109/APCCAS55924.2022.10090392","DOIUrl":"https://doi.org/10.1109/APCCAS55924.2022.10090392","url":null,"abstract":"In this work, we present a change point detection (CPD) method to detect abrupt changes in time-series data obtained from complex systems such as large scale networks. The proposed method works by converting the original time-series into binary-valued sequences with Os and 1s and then identifying the time instances that the density of 1s change. Under a mild assumption that the 0/1 samples are drawn from the same distribution in both reference and test period, we develop a double-direction detection method to detect upward and downward change of the density of 1-samples. The proposed CPD method is applied to operate at both fast and slow time scales to detect changes that last for shorter and longer durations. Numerical results obtained from time-series dataset of large scale cellular network are used to evaluate the performance of the proposed method.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115919429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Hybrid Method for Signal Probability Estimation with Combinational Circuits 一种组合电路信号概率估计的混合方法
2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2022-11-11 DOI: 10.1109/APCCAS55924.2022.10090301
Chunhong Chen, Suoyue Zhan
{"title":"A Hybrid Method for Signal Probability Estimation with Combinational Circuits","authors":"Chunhong Chen, Suoyue Zhan","doi":"10.1109/APCCAS55924.2022.10090301","DOIUrl":"https://doi.org/10.1109/APCCAS55924.2022.10090301","url":null,"abstract":"Signal probability is one of the most important factors in evaluating the performance of digital circuits. However, estimating signal probability for large circuits could be difficult due to signal delay and/or complex signal correlations caused by reconvergent fanouts. In this paper, we propose a hybrid approach to estimate signal probability by categorizing the strength of signal correlations in order to propagate signal probabilities through logic gates. Probabilities for signals with strong correlation are calculated directly and accurately, while those with relatively-weak correlations are evaluated using local bit-stream simulations. Simulation results on benchmark circuits show that the proposed method is both efficient and effective with a high level of accuracy.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117194058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 60V Input Integrated 3-to-1 Dual Inductor Hybrid Dickson Converter 60V输入集成3对1双电感混合迪克森转换器
2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2022-11-11 DOI: 10.1109/APCCAS55924.2022.10090294
Quyet Nguyen, Huy-Dung Han, L. Pham-Nguyen, Hanh-Phuc Le
{"title":"A 60V Input Integrated 3-to-1 Dual Inductor Hybrid Dickson Converter","authors":"Quyet Nguyen, Huy-Dung Han, L. Pham-Nguyen, Hanh-Phuc Le","doi":"10.1109/APCCAS55924.2022.10090294","DOIUrl":"https://doi.org/10.1109/APCCAS55924.2022.10090294","url":null,"abstract":"This paper presents a design of dual inductor hybrid (DIH) converter based on a 3-to-1 hybrid Dickson converter with fully on-chip control system and power switches for high-input-voltage and high-conversion-ratio applications. Using a 180-nm high-voltage CMOS technology, the converter reaches ~93% peak efficiency at 6W output power and an output range from 3.3V to 9V for an input range from 48V to 60V.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117335526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Multi-modal Asymmetric Autoencoders for Massive Photo Collection Applications 用于大规模照片收集应用的多模态非对称自动编码器
2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2022-11-11 DOI: 10.1109/APCCAS55924.2022.10090330
Aymen Hamrouni, Hakim Ghazzai, Y. Massoud
{"title":"Multi-modal Asymmetric Autoencoders for Massive Photo Collection Applications","authors":"Aymen Hamrouni, Hakim Ghazzai, Y. Massoud","doi":"10.1109/APCCAS55924.2022.10090330","DOIUrl":"https://doi.org/10.1109/APCCAS55924.2022.10090330","url":null,"abstract":"There has been an abundant use of applications where many photos obtained from camera-equipped devices can be leveraged and exploited to enable emerging services, e.g., mobile crowdsourcing. These systems usually collect a large data stream of images coming from different heterogeneous sources (e.g, IoT devices and humans) in an inadvertent way. Due to the limitations and challenges related to communication bandwidth, storage, and processing capabilities, it is unwise to transfer unselectively all the photos since most of them often either contain duplicate information, are inaccurate, or are just falsely submitted. In this paper, we propose to design a smart image selection procedure using an asymmetric multi-modal neural network autoencoder to select a subset of photos that has high utility coverage for multiple incoming streams. The proposed system enables selecting high context data from an evolving picture stream and ensures relevance. The approach uses the photo's metadata such as geo-location and timestamps along with the pictures' semantics to decide which photos can be submitted and which ones must be discarded. Simulation results for two different multi-modal autoencoder architectures indicate that a mixed asymmetric stacked autoencoder approach can yield better results outperforming the concatenated input autoencoder while leveraging user-side rendering to reduce bandwidth consumption and computational overhead.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122582949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 0.004-mm2 O.7-V 31.654-μW BPSK Demodulator Incorporating Dual-Path Loop Self-Biased PLL 一种0.004 mm2 0.7 v 31.654 μ w双路自偏置锁相环BPSK解调器
2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2022-11-11 DOI: 10.1109/APCCAS55924.2022.10090331
Yixi Li, Xinyu Shen, Zhao Zhang, Guike Li, Tao Yin, Nan Qi, Jian Liu, N. Wu, Liyuan Liu, Yong Chen, Zhao Zhang
{"title":"A 0.004-mm2 O.7-V 31.654-μW BPSK Demodulator Incorporating Dual-Path Loop Self-Biased PLL","authors":"Yixi Li, Xinyu Shen, Zhao Zhang, Guike Li, Tao Yin, Nan Qi, Jian Liu, N. Wu, Liyuan Liu, Yong Chen, Zhao Zhang","doi":"10.1109/APCCAS55924.2022.10090331","DOIUrl":"https://doi.org/10.1109/APCCAS55924.2022.10090331","url":null,"abstract":"This paper presents a low-supply binary-phase-shift-keying (BPSK) demodulator based on an area- and power-efficiency phase-locked loop (PLL) for wireless power biomedical implants with high-quality factor (Q) coils. The dual-path loop self-biased PLL is proposed to reduce the area of the integral capacitor and is insensitive to the process, voltage, and temperature (PVT) variations. Hence, our PLL can be designed with a wide loop bandwidth to increase the maximum input data rate of the demodulator. Designed in a 40-nm CMOS process with a tiny core area of 0.004 mm2, our BPSK demodulator merely consumes 31.654 μW with a 0.7-V supply voltage. Simulations show that our BPSK demodulator can deliver at the maximum data rate of 847.5 kb/s operating at a 13.56-MHz carrier frequency under different process corners.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124784172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An Energy-Efficient Readout Circuit Based on Incremental Delta-Sigma ADC with Decimation Filter for CMOS Image Sensors 基于增量δ - σ ADC和抽取滤波器的CMOS图像传感器节能读出电路
2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2022-11-11 DOI: 10.1109/APCCAS55924.2022.10090386
Junsheng Chen, Lingxin Meng, Menglian Zhao, Z. Tan
{"title":"An Energy-Efficient Readout Circuit Based on Incremental Delta-Sigma ADC with Decimation Filter for CMOS Image Sensors","authors":"Junsheng Chen, Lingxin Meng, Menglian Zhao, Z. Tan","doi":"10.1109/APCCAS55924.2022.10090386","DOIUrl":"https://doi.org/10.1109/APCCAS55924.2022.10090386","url":null,"abstract":"This paper presents an energy-efficient readout circuit based on incremental delta-sigma ADC (IADC) with a decimation filter for CMOS image sensors (CIS). A single-end 3rd-order 1-bit inverter-based delta-sigma ADC is embedded to achieve high resolution conversion efficiently. In addition, the correlated level shifting (CLS) technique was adopted, which enhances the DC gain of the integrator from 42.7 dB to 62.4 dB and extends the output swing from 85% to 100% of the full scale. A compact decimation filter with digital correlation double sampling (CDS) was used, which consists of only a counter and two digital integrators. The prototype chip is designed in a 55 nm CMOS process with a 1.2V supply voltage. Transient noise post-simulation results reveal the decimation filter consumes $boldsymbol{33.0} mumathbf{W}$ and the IADC consumes $boldsymbol{30.2} mu mathbf{W}$ while achieving 82.8 dB SNR in 25 $boldsymbol{mu}mathbf{s}$ conversion time, resulting in a Schreier FoM of 171.0 dB.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130021175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Dynamic JPEG CODEC with Adaptive Quantization Table for Frame Storage Compression 基于自适应量化表的动态JPEG编解码器
2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2022-11-11 DOI: 10.1109/APCCAS55924.2022.10090323
Yicheng Ouyang, Xianglong Wang, Gang Shi, Lei Chen, F. An
{"title":"A Dynamic JPEG CODEC with Adaptive Quantization Table for Frame Storage Compression","authors":"Yicheng Ouyang, Xianglong Wang, Gang Shi, Lei Chen, F. An","doi":"10.1109/APCCAS55924.2022.10090323","DOIUrl":"https://doi.org/10.1109/APCCAS55924.2022.10090323","url":null,"abstract":"Joint Photographic Experts Group (JPEG) is one of the most advanced compression formats for still images. However, JPEG is still limited and inefficient in real-time image processing and hardware implementation. This paper presents a dynamic JPEG CODEC (the encoder and decoder) to compress the frame storage. Based on the pipeline structure, the system uses ping-pong buffers to support the circuit across two clock domains. In addition, through dynamically adjusting the quantization table, the frame storage compression can fluctuate around 80% with high quality. Also, the simplification of compression decreases the initialization time of the decoder. The proposed word can yield a reduction of the frame storage of 76.60% and an improvement of the latency of 77.10% compared to the baseline JPEG CODEC.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"102 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134096611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design of SEL Self-Recovery Hardness for 90nm COTS Devices Using R-C-S Network with DC-DC Converter 基于R-C-S网络和DC-DC变换器的90nm COTS器件SEL自恢复硬度设计
2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2022-11-11 DOI: 10.1109/APCCAS55924.2022.10090280
Jindou Xin, Xiang Zhu, Yingqi Ma, Jianwei Han
{"title":"Design of SEL Self-Recovery Hardness for 90nm COTS Devices Using R-C-S Network with DC-DC Converter","authors":"Jindou Xin, Xiang Zhu, Yingqi Ma, Jianwei Han","doi":"10.1109/APCCAS55924.2022.10090280","DOIUrl":"https://doi.org/10.1109/APCCAS55924.2022.10090280","url":null,"abstract":"An efficient Single Event Latch-up (SEL) self-recovery hardness design using an R-C-S network in the front of a DC-DC converter is proposed in this brief. Conventional SEL hardness assurance is suffering from increased circuit design area and low reliability of the COTS devices. To overcome these problems., the proposed design makes a further contribution to the hardness of SEL. The operational mechanism of the proposed design is that the R-C-S network changes the latch-up voltage of the device through the intrinsic properties of the DC-DC converter. The latch-up voltage is carried through three phases of dropping, oscillation and rising, enabling the device to implement hardness and self-recovery. Meanwhile, simulation and laser tests are employed to demonstrate the validity of the proposed method. Additionally, through comparison with conventional hardness designs of power-off restarting and current limiting by resistor, it is evidently observed that the proposed method has current continuity characteristics and uses 5 components instead of 11 for power-off restarting. And the proposed method effectively exits the device from SEL and reduces the error bits by 72.2% compared to conventional resistor hardness.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132308369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 300-GHz Wideband Injection Locked Frequency Quadrupler in 250-nm InP DHBT Technology 250纳米InP DHBT技术中的300 ghz宽带注入锁频四倍器
2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2022-11-11 DOI: 10.1109/APCCAS55924.2022.10090284
Surajit Kumar Nath, Daekeun Yoon
{"title":"A 300-GHz Wideband Injection Locked Frequency Quadrupler in 250-nm InP DHBT Technology","authors":"Surajit Kumar Nath, Daekeun Yoon","doi":"10.1109/APCCAS55924.2022.10090284","DOIUrl":"https://doi.org/10.1109/APCCAS55924.2022.10090284","url":null,"abstract":"A sub-THz band frequency quadrupler with a frequency range of 250 to 350 GHz is presented in this paper using 250-nm InP DHBT technology. The circuit employs a D-band frequency doubler with an H-band injection-locked push-push oscillator to produce x4 frequency. A collector-to-base feedback technique is introduced to boost the harmonic output power of the injection-locked push-push Colpitts oscillator. The proposed quadrupler showed 4th harmonic peak output power of −3.3 dBm and 1.75 % DC-RF efficiency at 328-GHz.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115423273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信