Chaotic Sampling of Double Scroll Chaos for Digital Random Number Generation

This article introduces a random number generator based on chaotic oscillators. Digitally obtained double scroll chaos was used as the basis for RNG design. The RNG is implemented on FPGA at the register transfer level using the third order ordinary differential equation to generate double scroll chaos. The 5-bit signed integer of a 32-bit fixed point number was used in the implementation. A signal that featured chaotic characteristics was used as a source and another chaotic signal was employed to sample the source signal to generate random bits. The random number generator that has been suggested is built using Verilog hardware description language and experimentally demonstrated on a Xilinx Virtex VC707 FPGA. The collected binary bits were subjected to the FIPS 140–2 randomness test suite and passed the tests successfully.