Hierarchical and Recursive Floorplanning Algorithm for NoC-Bascd Scalable Multi-Die FPGAs

Emerging applications are calling for significantly larger FPGAs with multi-dies. However, these multi-die FPGAs with a traditional substrate-based interconnection are not scalable enough, because the execution time and probability of failure of their floorplanning algorithm will increase dramatically with the growth of design or the number of ides. Therefore, future multi-die FPGAs will require a scalable interconnection architecture and its associated floorplanning algorithm. To address this issue, we propose both a new NoC-based scalable multi-die FPGA architecture and a corresponding floorplanning algorithm, namely Hierarchical and Recursive Floorplanning Algorithm(HRFA). First, we introduce the interconnection architecture with a class of scalable hierarchical topologies. Second, we formulate the floorplanning problem for the proposed NoC architecture as an ILP (Integer Linear Programming). Third, we develop a novel recursive method to solve the ILP formulation by taking advantage of the parallelization opportunities exploited from the hierarchical interconnection architectures. The experiments on a Convolutional Neural Network (CNN) benchmark show that the scalability of our proposed technique is at least $3\times$ as that of the state-of-the-art solutions measured by the size of the feasible benchmark, with no loss of design performance.