A 500-MHz 32-bit DETFF-based Shift Register Utilizing 40-nm CMOS Technology

A double-edge triggered flip-flop (DETFF) has the distinct ability to latch data at either the rising or the falling edge of the edge unlike the single-edge triggered flip-flop (SETFF). The proposed DETFF uses parallel dual paths that work without the need of keepers for input signal boost and an inverting clock for the opposite phase operation. A Schmitt trigger replaced the conventional feedback inverter with keeper in the DETFF, since the feedback inverter may lead to metastability which can affect the output at unexpected timing. The said DETFF was implemented in a 32-bit shift register using TSMC 40-nm CMOS for functionality testing. At a load capacitance of 60 pF, 31.71% power consumption decrease and 43.57% Tc-q delay reduction were exhibited by the proposed shift register as shown by the post-layout simulation results. It has the best normalized energy per bit normalized power, and normalized delay per bit among prior works.