A 500-MS/s 9-Bit Time-Domain ADC Using a Nonbinary Successive Approximation TDC

This paper presents a 500-MS/s 9-bit time-domain analog-to-digital converter (ADC) using a nonbinary successive approximation time-to-digital converter (SA TDC) for energy efficiency and high linearity. By adding redundancy in the first six decision steps, the delay fluctuations of the delay cells and offset of the time-domain comparators in the SA TDC can be tolerated and nonlinearity can thus be reduced. In addition, a voltage-to-time converter (VTC) with a voltage-boost scheme is utilized to expand the linear dynamic range. Simulated in 28nm CMOS, the time-domain ADC consumes 4.27 mW under supply voltages of 0.9 V and 2.5 V. It is shown that SNDR and SFDR are 54.69 dB and 55.16 dB at Nyquist input frequency operating at a 500-MS/s sampling rate, respectively, resulting in a Walden figure of merit (FOMw) of 19.29 fJ/conversion step.